DSPIC30F3010-30I/SO

Key features

• Modified Harvard Architecture
• C Compiler Optimized Instruction Set Architecture with Flexible Addressing modes
• 83 Base Instructions
• 24-bit Wide Instructions, 16-bit Wide Data Path
• 24 Kbytes On-Chip Flash Program Space (8K instruction words)
• 1 Kbyte of On-Chip Data RAM
• 1 Kbyte of Nonvolatile Data EEPROM
• 16 x 16-bit Working Register Array
• Up to 30 MIPs Operation: DC to 40 MHz external clock input; 4 MHz - 10 MHz oscillator input with PLL active (4x, 8x, 16x)
• 29 Interrupt Sources: 3 external interrupt sources; 8 user-selectable priority levels for each interrupt source; 4 processor trap sources
• Dual Data Fetch
• Accumulator Write Back for DSP Operations
• Modulo and Bit-Reversed Addressing modes
• Two, 40-bit Wide Accumulators with Optional saturation Logic
• 17-bit x 17-bit Single-Cycle Hardware Fractional/ Integer Multiplier
• All DSP Instructions Single Cycle
• ±16-bit Single-Cycle Shift
• High-Current Sink/Source I/O Pins: 25 mA/25 mA
• Timer module with Programmable Prescaler: Five 16-bit timers/counters; optionally pair 16-bit timers into 32-bit timer modules