DSPIC30F4011-30I/PT

Key features

• Modified Harvard architecture
• C compiler-optimized ISA with flexible addressing modes
• 83 base instructions
• 24-bit wide instruction, 16-bit wide data bus
• 48 KB on-chip Flash program space (16K instruction words)
• 2 KB on-chip data RAM
• 1 KB non-volatile data EEPROM
• Up to 30 MIPS operating speed:
• DC to 40 MHz external clock input
• 4 MHz–10 MHz oscillator input with PLL (4x, 8x, and 16x)
• 30 interrupt sources:
• 3 external interrupt sources
• 8 user-selectable interrupt priority levels per interrupt source
• 4 processor trap sources
• 16 x 16-bit working register array
• Dual data fetch operations
• Accumulator write-back for DSP operations
• Modulo and bit-reversed addressing modes
• Two 40-bit accumulators with optional saturation logic
• 17-bit x 17-bit single-cycle hardware fractional/integer multiplier
• All DSP instructions single-cycle
• Single-cycle ±16-bit shift
• High sink/source current I/O pins: 25 mA/25 mA
• Timer module with programmable prescaler:
• Five 16-bit timer/counters; 16-bit timers can be paired to form 32-bit timer modules
• 16-bit input capture
• 16-bit compare/PWM output
• 3-wire SPI module (supports 4 frame modes)
• I²C module supporting multi-master/slave mode with 7-bit/10-bit addressing
• 2 UART modules with FIFO buffers
• CAN module compatible with 2.0B standard
• 6-channel PWM output:
• Complementary or independent output modes
• Edge-aligned and center-aligned modes
• 3 duty cycle generators
• Dedicated time base
• Programmable output polarity
• Dead-time control for complementary mode
• Manual output control
• Trigger for A/D conversion
• Phase A, Phase B, and index pulse inputs
• 16-bit up/down position counter
• Count direction status
• Position measurement (x2 and x4) modes
• Programmable digital noise filter on inputs
• Alternate 16-bit timer/counter mode
• Position counter overflow/underflow interrupt
• 10-bit ADC with 4 sample-and-hold (S&H) inputs:
• 1 Msps conversion rate
• 9 input channels
• Conversion during Sleep and Idle
• Programmable brown-out reset
• Enhanced Flash program memory:
• Industrial temperature range: 10,000 erase/write cycles minimum, 100,000 typical
• Data EEPROM memory:
• Industrial temperature range: 100,000 erase/write cycles minimum, 1,000,000 typical
• Self-reprogrammable under software control
• POR, PWRT, and OST
• Flexible WDT with on-chip low-power RC oscillator for reliable operation
• Fail-safe clock monitor detects clock failure and switches to on-chip low-power RC oscillator
• Programmable code protection
• ICSP
• Selectable power management modes:
• Sleep, Idle, and Alternate Clock modes
• Low-power high-speed Flash technology
• Wide operating voltage range (2.5V to 5.5V)
• Industrial and extended temperature ranges
• Low power