DSPIC30F4012-30I/SO

Key features

• Modified Harvard architecture
• C compiler optimized instruction set architecture with flexible addressing modes
• 83 base instructions
• 24-bit wide instructions, 16-bit wide data path
• 48 Kbytes on-chip Flash program space (16K instruction words)
• 2 Kbytes of on-chip data RAM
• 1 Kbyte of nonvolatile data EEPROM
• Up to 30 MIPS operation: DC to 40 MHz external clock input; 4 MHz - 10 MHz oscillator input with PLL active (4x, 8x, 16x)
• 30 interrupt sources: Three external interrupt sources; Eight user-selectable priority levels for each interrupt source; Four processor trap sources
• 16x16-bit working register array
• Dual data fetch
• Accumulator write-back for DSP operations
• Modulo and Bit-Reversed Addressing modes
• Two, 40-bit wide accumulators with optional saturation logic
• 17-bit x 17-bit single-cycle hardware fractional/integer multiplier
• All DSP instructions are single cycle
• ±16-bit, single-cycle shift
• High-current sink/source I/O pins: 25 mA/25 mA
• Timer module with programmable prescaler: Five 16-bit timers/counters; optionally pair 16-bit timers into 32-bit timer modules
• 16-bit Capture input functions