DSPIC30F4013-20E/PT

Key features

• Modified Harvard Architecture
• C Compiler Optimized Instruction Set Architecture
• Flexible Addressing modes
• 83 Base Instructions
• 24-Bit Wide Instructions, 16-Bit Wide Data Path
• Up to 48 Kbytes On-Chip Flash Program Space
• 2 Kbytes of On-Chip Data RAM
• 1 Kbyte of Nonvolatile Data EEPROM
• 16 x 16-Bit Working Register Array
• Up to 30 MIPS Operation: DC to 40 MHz External Clock Input; 4 MHz - 10 MHz Oscillator Input with PLL Active (4x, 8x, 16x)
• Up to 33 Interrupt Sources: 8 user-selectable priority levels; 3 external interrupt sources; 4 processor traps
• Dual Data Fetch
• Modulo and Bit-Reversed modes
• Two 40-Bit Wide Accumulators with Optional saturation Logic
• 17-Bit x 17-Bit Single-Cycle Hardware Fractional/Integer Multiplier
• All DSP Instructions are Single Cycle - Multiply-Accumulate (MAC) Operation
• Single-Cycle ±16 Shift
• High-Current Sink/Source I/O Pins: 25 mA/25 mA
• Up to Five 16-Bit Timers/Counters; Optionally Pair Up 16-Bit Timers into 32-Bit Timer modules
• Up to Four 16-Bit Capture Input Functions
• Up to Four 16-Bit Compare/PWM Output Functions
• Data Converter Interface (DCI) Supports Common Audio Code