dsPIC33CH256MP506-I/PT

TQFP-64(10x10) Microcontrollers RoHS

TQFP-64(10x10)ROHS3 CompliantActive

Dual Core, 16-Bit Digital Signal Controllers with High-Resolution PWM and CAN Flexible Data-Rate (CAN FD)

Manufacturer: MICROCHIP
Manufacturer part #: dsPIC33CH256MP506-I/PT
Store part #: C619271
Package / case: TQFP-64(10x10)
Category: Microcontrollers
Packaging: Tray

Datasheet (PDF)

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100% Authentic · 30-Day Return or Replacement · policy

5 in stock

#C619271

Stock & price checked 5 days ago

Quantity	Unit price	Pack price
1+	₹774.75	₹774.75
10+	₹756.07	₹7,560.70
30+	₹743.68	₹22,310.40
100+	₹731.30	₹73,130.00

Quantity (min 1)

1 × ₹774.75

₹774.75

excl. GST

₹914.21 incl. 18% GST

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Standard pack: 160 per tray

dsPIC33CH256MP506-I/PT

₹774.75 for 1 + GST

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Specifications

Operating Temperature: -40℃~+85℃

Packaging & compliance

RoHS: ROHS3 Compliant
Lifecycle: Active
ECCN: 3A991A2
Packaging: Tray
Standard pack: 160 / Tray
Sold per: Piece
Minimum order: 1
Unit weight: 1.14 g

Overview

Applications

DC/DC Converters
AC/DC power supplies
Uninterruptable Power Supply (UPS)
Motor Control: BLDC, PMSM, SR, ACIM

Key features

Master/Slave Core Operation
Independent Peripherals for Master Core and Slave Core
Configurable Shared Resources for Master Core and Slave Core
Master Core with 256 - 512 Kbytes of Program Flash with ECC and 32 - 48K Data RAM with BIST
Slave Core with 72 Kbytes of Program RAM (PRAM) with ECC and 16K Data RAM with BIST
Fast 6 - Cycle Divide
LiveUpdate
Message Boxes and FIFO to Communicate Between Master and Slave (MSI)
Code Efficient (C and Assembly) Architecture
40 - Bit Wide Accumulators
Single - Cycle (MAC/MPY) with Dual Data Fetch
Single - Cycle, Mixed - Sign MUL Plus Hardware Divide
32 - Bit Multiply Support
Five Sets of Interrupt Context Selected Registers per Core for Fast Interrupt Response
Zero Overhead Looping
Internal Oscillator
Programmable PLLs and Oscillator Clock Sources
Master Reference Clock Output
Slave Reference Clock Output
Fail - Safe Clock Monitor (FSCM)
Fast Wake - up and Start - up
Backup Internal Oscillator
LPRC Oscillator
Low - Power Management Modes (Sleep, Idle, Doze)
Integrated Power - on Reset and Brown - out Res
Up to Twelve PWM Channels: Four channels for Master, Eight channels for Slave
250 ps PWM Resolution
Two General Purpose 16 - Bit Timers: One each for Master and Slave
Peripheral Trigger Generator (PTG) Module: One module for Master, Slave can interrupt on select PTG sources, Useful for automating complex sequences
Twelve SCCP Modules: Eight modules for Master, Four modules for Slave, Timer, Capture/Compare and PWM modes, 16 or 32 - bit time base, 16 or 32 - bit capture, 4 - deep capture buffer, Fully asynchronous operation, available in Sleep modes
Four ADC Modules: One module for Master core, Three modules for Slave core, 12 - bit, 3.25 Msps ADC, Up to 18 conversion channels, 250 ns conversion latency
Four DAC/Analog Comparator Modules: One module for Master core, Three modules for Slave core, 12 - bit DACs with hardware slope compensation, 15 ns analog comparators
Three PGA Modules: Three modules for Slave core, Can be read by Master ADC
Shared DAC/Analog Output: DAC/analog comparator outputs, PGA outputs
Three UART Modules: Two modules for Master core, One module for Slave core, Support for DMX, LIN/J2602 protocols
Three 4 - Wire SPI/I²S Modules: Two modules for Master core, One module for Slave core
Two CAN Flexible Data - Rate (FD) Modules for the Master Core
Three I²C Modules: Two modules for Master, One module for Slave, Support for SMBus
PPS to Allow Function Remap
Programmable Cyclic Redundancy Check (CRC) for the Master
Two SENT Modules for the Master
Eight DMA Channels: Six DMA channels available for the Master core, Two DMA channels available for the Slave core
In - Circuit and In - Application Programming
Simultaneous Debugging Support for Master and Slave Cores
Master Only Debug and Slave Only Debug Support
Master with Three Complex, Five Simple Breakpoints and Slave with One Complex, Two Simple Breakpoints
IEEE 1149.2 Compatible (JTAG) Boundary Scan
Trace Buffer and Run - Time Watch
DMT (Deadman Timer)
ECC (Error Correcting Code)
WDT (Watchdog Timer)
CodeGuard Security
CRC (Cyclic Redundancy Check)
ICSP Write Inhibit
RAM Memory Built - In Self Test (MBIST)
Two - Speed Start - up
Fail - Safe Clock Monitoring (FSCM)
Backup FRC (BFRC)
Capless Internal Voltage Regulator
Virtual Pins for Redundancy and Monitoring
AEC - Q100 REVG (Grade 1: - 40℃ to + 125℃) Compliant
Class B Safety Library, IEC 60730