dsPIC33EP128GS708-I/PT

TQFP-80(12x12) Microcontrollers RoHS

TQFP-80(12x12)ROHS3 CompliantActive

16-Bit Digital Signal Controllers for Digital Power Applications with Interconnected High-Speed PWM, ADC, PGA and Comparators

Manufacturer: MICROCHIP
Manufacturer part #: dsPIC33EP128GS708-I/PT
Store part #: C635452
Package / case: TQFP-80(12x12)
Category: Microcontrollers
Packaging: Tray

Datasheet (PDF)

Every Order Guarantee

100% Authentic · 30-Day Return or Replacement · policy

4 in stock

#C635452

Stock & price checked 3 days ago

Quantity	Unit price	Pack price
1+	₹1,791.10	₹1,791.10
10+	₹1,732.35	₹17,323.50

Quantity (min 1)

1 × ₹1,791.10

₹1,791.10

excl. GST

₹2,113.50 incl. 18% GST

Need volume or a scheduled delivery? Request a quote

Dispatch in 15-18 working days
GST invoice with every order
Standard pack: 119 per tray

dsPIC33EP128GS708-I/PT

₹1,791.10 for 1 + GST

Need this with the rest of your board? Upload the BOM — we price every line.Upload BOM

Specifications

Operating Temperature: -40℃~+85℃

Packaging & compliance

RoHS: ROHS3 Compliant
Lifecycle: Active
ECCN: 3A991A2
Packaging: Tray
Standard pack: 119 / Tray
Sold per: Piece
Minimum order: 1
Unit weight: 7.35 g

Overview

Applications

AC/DC
DC/DC
Inverters
PFC
Lighting

Key features

Code-Efficient (C and Assembly) Architecture
Two 40-Bit Wide Accumulators
Single-Cycle (MAC/MPY) with Dual Data Fetch
Single-Cycle Mixed-Sign MUL plus Hardware Divide
32-Bit Multiply Support
Four Additional Working Register Sets (reduces context switching)
±0.9% Internal Oscillator
Programmable PLLs and Oscillator Clock Sources
Fail-Safe Clock Monitor (FSCM)
Independent Watchdog Timer (WDT)
Fast Wake-up and Start-up
Low-Power Management modes (Sleep, Idle, Doze)
Integrated Power-on Reset and Brown-out Reset
0.5 mA/MHz Dynamic Current (typical)
20 μA IPD Current (typical)
Eight PWM Generators (two outputs per generator)
Individual Time Base and Duty Cycle for each PWM
1.04 ns PWM Resolution (frequency, duty cycle, dead time and phase)
Supports Center-Aligned, Redundant, Complementary and True Independent Output modes
Independent Fault and Current-Limit Inputs
Output Override Control
12-bit with four dedicated SAR ADC cores and one shared SAR ADC core
Configurable resolution (up to 12-bit) for each ADC core
Up to 3.25 Msps conversion rate per channel at 12-bit resolution
11 to 22 single-ended inputs
Dedicated result buffer for each analog channel
Flexible and independent ADC trigger sources
Two digital comparators
Two oversampling filters for increased resolution
Four Rail-to-Rail Comparators with Hysteresis
Dedicated 12-bit Digital-to-Analog Converter (DAC) for each analog comparator
Up to two DAC reference outputs
Up to two external reference inputs
Two Programmable Gain Amplifiers
Single-ended or independent ground reference
Five selectable gains (4x, 8x, 16x, 32x and 64x)
40 MHz gain bandwidth
Reduces CPU Interaction to Improve Performance
Flexible PWM Trigger Options for ADC Conversions
High-Speed Comparator Truncates PWM (15 ns typical)
Supports Cycle-by-Cycle Current-mode control
Current Reset mode (variable frequency)
Five 16-Bit and up to Two 32-Bit Timers/Counters
Four Output Compare (OC) modules, Configurable as Timers/Counters
Four Input Capture (IC) modules
Two UART modules (15 Mbps)
Supports LIN/J2602 protocols and IrDA
Three Variable Width SPI modules with Operating modes
3-wire SPI
8x6 or 8x8 FIFO mode
I2S mode
Two I2C modules (up to 1 Mbaud) with SMBus Support
Up to Two CAN modules
Four-Channel DMA
Constant-Current Source (10 μA nominal)
Sink/Source up to 12 mA/15 mA, respectively; Pin-Specific for Standard VOH/VOL
5V Tolerant Pins
Selectable, Open-Drain Pull-ups and Pull-Downs
External Interrupts on all I/O Pins
Peripheral Pin Select (PPS) to allow Function Remap with Six Virtual I/Os
AEC-Q100 REVG (Grade 1, -40℃ to +125℃)
Class B Safety Library, IEC 60730
The 6x6x0.55 mm UQFN Package is Designed and Optimized to ease IPC9592B 2nd Level Temperature Cycle Qualification
In-Circuit and In-Application Programming
Five Program and Three Complex Data Breakpoints
IEEE 1149.2 Compatible (JTAG) Boundary Scan
Trace and Run-Time Watch
Four Configurable Logic Cells
Peripheral Trigger Generator