Varnitronics
DSPIC33FJ256GP710-I/PT MICROCHIP
MICROCHIP

DSPIC33FJ256GP710-I/PT

TQFP-100(12x12) Microcontrollers RoHS

TQFP-100(12x12)ROHS3 CompliantActive

16-Bit Digital Signal Controllers

Manufacturer
MICROCHIP
Manufacturer part #
DSPIC33FJ256GP710-I/PT
Store part #
C61579
Package / case
TQFP-100(12x12)
Packaging
Tray
Datasheet (PDF)

Every Order Guarantee

100% Authentic · 30-Day Return or Replacement · policy

26 in stock

#C61579

Stock & price checked 7 days ago

QuantityUnit pricePack price
1+₹1,818.34₹1,818.34
10+₹1,790.96₹17,909.60
30+₹1,743.81₹52,314.30
100+₹1,702.53₹1,70,253.00

1 × ₹1,818.34

₹1,818.34

excl. GST

₹2,145.64 incl. 18% GST

Need volume or a scheduled delivery? Request a quote
  • Dispatch in 15-18 working days
  • GST invoice with every order
  • Standard pack: 119 per tray

DSPIC33FJ256GP710-I/PT

₹1,818.34 for 1 + GST

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Specifications

Operating Temperature
-40℃~+85℃

Packaging & compliance

RoHS
ROHS3 Compliant
Lifecycle
Active
ECCN
3A991A2
Packaging
Tray
Standard pack
119 / Tray
Sold per
Piece
Minimum order
1
Unit weight
1.815 g

Overview

Key features

  • Up to 40 MIPS operation (at 3.0 - 3.6V): Industrial temperature range (-40°C to +85°C)
  • Modified Harvard architecture
  • C compiler optimized instruction set
  • 16-bit wide data path
  • 24-bit wide instructions
  • Linear program memory addressing up to 4M instruction words
  • Linear data memory addressing up to 64 Kbytes
  • 83 base instructions: mostly 1 word/1 cycle
  • Sixteen 16-bit General Purpose Registers
  • Two 40-bit accumulators: With rounding and saturation options
  • Flexible and powerful addressing modes: Indirect, Modulo and Bit-Reversed
  • Software stack
  • 16x16 fractional/integer multiply operations
  • 32/16 and 16/16 divide operations
  • Single-cycle multiply and accumulate: Accumulator write back for DSP operations, Dual data fetch
  • Up to ±16-bit shifts for up to 40-bit data
  • 8-channel hardware DMA
  • 2 Kbytes dual ported DMA buffer area (DMA RAM) to store data transferred via DMA: Allows data transfer between RAM and a peripheral while CPU is executing code (no cycle stealing)
  • Most peripherals support DMA
  • 5-cycle latency
  • Up to 63 available interrupt sources
  • Up to five external interrupts
  • Seven programmable priority levels
  • Five processor exceptions
  • Up to 85 programmable digital I/O pins
  • Wake-up/Interrupt-on-Change on up to 24 pins
  • Output pins can drive from 3.0V to 3.6V
  • All digital input pins are 5V tolerant
  • 4 mA sink on all I/O pins
  • Flash program memory, up to 256

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