F280034SPN

The TMS320F28003x (F28003x) is a member of the C2000 RW real-time microcontroller family of scalable, ultralow latency devices design

Applications

• Appliances
• Air conditioner outdoor unit
• Building automation
• Door operator drive control
• Industrial machine & machine tools
• Automated sorting equipment
• Textile machine
• AC inverter & VF drives
• AC drive control module
• AC drive position feedback
• AC drive power stage module
• Linear motor transport systems
• Linear motor power stage
• Single & multi axis servo drives
• Servo drive position feedback
• Servo drive power stage module
• Speed controlled BLDC drives
• AC-input BLDC motor drive
• DC-input BLDC motor drive
• Factory automation
• Robot servo drive
• Mobile robot motor control
• Position sensor
• Industrial power
• Industrial AC-DC
• UPS
• Three phase UPS
• Single phase online UPS
• Telecom & server power
• Merchant DC/DC
• Merchant network & server PSU
• Merchant telecom rectifiers
• Hybrids, electric & powertrain systems
• DC/DC converter
• Inverter & motor control
• On-board (OBC) & wireless charger
• Virtual engine sound system (VESS)
• Engine fan
• eTurbo/charger
• Pump
• Electric power steering (EPS)
• Infotainment and cluster
• Head-up display
• Automotive head unit
• Automotive external amplifier
• Body electronics & lighting
• Automotive HVAC compressor module
• DC/AC inverter
• Headlight
• ADAS
• Mechanically scanning LIDAR
• HEV/EV battery-management system (BMS)
• 100-V battery pack-passive balancing
• 12- & 24-V battery pack-passive balancing
• 400-V battery pack-passive balancing
• 48-V battery pack-passive balancing
• EV charging infrastructure
• AC charging (pile) station
• DC charging (pile) station
• EV charging station power module
• Wireless EV charging station
• Renewable energy storage
• Energy storage power conversion system (PCS)
• Solar energy
• Central inverter
• Micro inverter
• Solar power optimizer
• Solar arc prot

Key features

• TMS320C28x 32-bit DSP core at 120 MHz
• IEEE 754 Floating-Point Unit (FPU)
• Support for Fast Integer Division (FINTDIV)
• Trigonometric Math Unit (TMU)
• Support for Nonlinear Proportional Integral Derivative (NLPID) control
• CRC Engine and Instructions (VCRC)
• Ten hardware breakpoints (with ERAD)
• Programmable Control Law Accelerator (CLA) 120 MHz IEEE 754 single-precision floating-point instructions
• Executes code independently of main CPU
• On-chip memory 384KB (192KW) of flash (ECC-protected) across three independent banks
• 69KB (34.5KW) of RAM (ECC-protected)
• Security: JTAGLOCK, Zero-pin boot, Dual-zone security
• Clock and system control: Two internal 10-MHz oscillators, Crystal oscillator or external clock input, Windowed watchdog timer module, Missing clock detection circuitry, Dual-clock Comparator (DCC)
• 3.3-V I/O design: Internal VREG generation allows for single-supply design, Brownout reset (BOR) circuit
• System peripherals: 6-channel Direct Memory Access (DMA) controller, 55 individually programmable multiplexed General-Purpose Input/Output (GPIO) pins, 23 digital inputs on analog pins, 2 digital inputs/outputs on analog pins (AGPIO), Enhanced Peripheral Interrupt Expansion (ePIE), Multiple low-power mode (LPM) support, Embedded Real-time Analysis and Diagnostic (ERAD), Unique Identification (UID) number
• Communications peripherals: One Power-Management Bus (PMBus) interface, Two Inter-integrated Circuit (I2C) interfaces, One Controller Area Network (CAN/DCAN) bus port, One Controller Area Network with Flexible Data-Rate (CAN FD/MCAN) bus port, Two Serial Peripheral Interface (SPI) ports, Two UART-compatible Serial Communication Interface (SCI), Two UART-compatible Local Interconnect Network (LIN) interfaces, Fast Serial Interface (FSI) with one transmitter and one receiver (up to 200Mbps)
• Analog system: Three 4-MSPS, 12-bit Analog-to-Digital Converters (ADCs), Up to 23 external channels (includes the two gpdac outputs), Four integrated Post-Processing Blocks (PPB) per ADC, Four windowed comparators (CMPSS) with 12-bit reference, Digital-to-Analog Converters (DACs), Digital glitch filters, Two 12-bit buffered DAC outputs
• Enhanced control peripherals: 16 ePWM channels with eight channels that have high-resolution capability (150-ps resolution), Integrated dead-band support, Integrated hardware trip zones (TZs), Three Enhanced Capture (eCAP) modules, High-resolution Capture (HRCAP) available on one of the three eCAP modules, Two Enhanced Quadrature Encoder Pulse (eQEP) modules with support for CW/CCW operation modes, Eight Sigma-Delta Filter Module (SDFM) input channels (two parallel filters per channel), Standard SDFM data filtering, Comparator filter for fast action for overvalue or undervalue condition, Embedded Pattern Generator (EPG)
• Configurable Logic Block (CLB): 4 tiles, Augments existing peripheral capability, Supports position manager solutions
• Host Interface Controller (HIC): Access to internal memory from an external host
• Background CRC (BGCRC): One cycle CRC computation on 32 bits of data
• Advanced Encryption Standard (AES) accelerator
• Live Firmware Update (LFU): Fast context switching from old to new firmware, Flash bank erase time improvements
• Diagnostic features: Memory Power On Self Test (MPOST), Hardware Built-in Self Test (HWBIST)
• Functional Safety-Compliant (PZ and Q100 PM packages only): Developed for functional safety applications, Documentation available to aid ISO 26262 and IEC 61508 system design, Systematic capability up to ASIL D and SIL 3, Hardware capability up to ASIL B and SIL 2
• Safety-related certification: ISO 26262 certification up to ASIL B and SIL 2 by TÜV SÜD (PZ and Q100 PM packages only)
• Package options: 100-pin Low-profile Quad Flatpack (LQFP) [PZ suffix], 80-pin Low-profile Quad Flatpack (LQFP) [PN suffix], 64-pin (LQFP) [PM suffix], 48-pin (LQFP) [PT suffix]
• Temperature options: Free-air (TA): -40℃ to 125℃, Junction (TJ): -40℃ to 150℃