F28P650DH6NMRR

NFBGA-169 Microcontrollers RoHS

NFBGA-169ROHS CompliantActive

Manufacturer: TI
Manufacturer part #: F28P650DH6NMRR
Store part #: C36165114
Package / case: NFBGA-169
Category: Microcontrollers
Packaging: Tape & Reel (TR)

Datasheet (PDF)

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3 in stock

#C36165114

Stock & price checked 3 days ago

Quantity	Unit price	Pack price
1+	₹2,702.81	₹2,702.81
10+	₹2,618.56	₹26,185.60

Quantity (min 1)

1 × ₹2,702.81

₹2,702.81

excl. GST

₹3,189.32 incl. 18% GST

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Standard pack: 1,000 per reel

F28P650DH6NMRR

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Packaging & compliance

RoHS: ROHS Compliant
Lifecycle: Active
ECCN: 5A992C
Packaging: Tape & Reel (TR)
Standard pack: 1,000 / Reel
Sold per: Piece
Minimum order: 1
Unit weight: 6.033 g

Overview

Applications

Servo drive control modules
Robotic servo drives
CNC control
Mobile robot motor control
HVAC large commercial motor control
Linear motor segmented controllers
Central inverters
String inverters
Power conversion systems
DC fast charging stations
Inverter and motor control
Industrial AC/DC conversion
Three-phase UPS
Single-phase online UPS
Commercial networking

Key features

Real-Time Processing: Up to three CPUs — two 32-bit C28x DSP CPUs and one CLA CPU, all running at 200MHz; real-time signal chain performance equivalent to the aggregate processing capability of a 1000MHz Arm Cortex-M7-based device; C28x DSP architecture features IEEE 754 double-precision (64-bit) FPU, Trigonometric Math Unit (TMU), Fast Integer Division (FINTDIV), CRC engine and instructions (VCRC); Control Law Accelerator (CLA) CPU supports IEEE 754 single-precision floating-point and executes code independently of the C28x CPU.
Memory: 1.28MB CPU-mappable flash (ECC-protected) organized into 5 flash banks; 248KB RAM (enhanced parity protection); External Memory Interface (EMIF) supporting ASRAM, SDRAM, or ASIC/FPGA.
Analog Subsystem: Three ADCs — 1.19MSPS each in 16-bit mode, 3.92MSPS each in 12-bit mode — with up to 40 single-ended or 19 differential inputs; independent sample-and-hold (S/H) per ADC for simultaneous sampling; hardware post-processing of conversions with hardware oversampling (up to 128×) and undersampling modes, accumulation, averaging, and outlier rejection; 24 redundant input channels for added flexibility; automatic comparison of conversion results for functional safety applications; 11 windowed comparators with 12-bit DAC reference featuring slope compensation for peak and valley current-mode control; internal temperature sensor and ADC reference connectivity options; two 12-bit buffered DAC outputs.
Control Peripherals: 36 PWM channels with 150ps high-resolution capability (HRPWM), supporting Minimum Dead Band Logic (MINDB), Illegal Combination Logic (ICL), and other special features (e.g., Diode Emulation [DE]); supports matrix converters, multilevel converters, and resonant converters without additional external logic; seven enhanced capture (eCAP) modules — two with High-Resolution Capture (HRCAP) — with two new monitoring units for edge, pulse width, and period, compatible with ePWM gating and trip events, 256 additional inputs for more capture options, new ADC SOC generation capability, and eCAP usable as additional PWM; six enhanced quadrature encoder pulse (eQEP) modules; 16 Sigma-Delta Filter Module (SDFM) input channels with 2 independent filters per channel; embedded pattern generator (EPG); Configurable Logic Block (CLB) with six logic cells to enhance existing peripheral capabilities or implement custom logic, reducing or eliminating external CPLD/FPGA, supporting encoder interfaces without FPGA and custom PWM generation for power conversion.
Communication Peripherals: EtherCAT Secondary (or Sub-) Device Controller (ESC); USB 2.0 (MAC + PHY); Fast Serial Interface (FSI) for up to 200Mbps data exchange across isolation; four high-speed (up to 50MHz) SPI ports; two SCI (UART-compatible); two high-speed (25Mbps) UART; two I²C (400Kbps); external boot options via SPI/SCI/I²C; two LIN modules compatible with UART (SCI-compatible); PMBus interface (I²C-compatible); one CAN/DCAN controller; two CAN FD/MCAN controllers with flexible data rate.
System Peripherals: Two 6-channel DMA controllers; 185 individually programmable multiplexed GPIO pins; expanded peripheral interrupt controller (ePIE); low-power mode (LPM) support; embedded real-time analysis and diagnostics (ERAD); background CRC (BGCRC).
Security Peripherals: AES (128/192/256) accelerator; JTAGLOCK, zero-pin boot, and dual-zone security support; unique identification (UID) number.
Safety-Related Peripherals: Simplified implementation via inverse comparison; C28x CPU2 with lockstep capability; Memory Power-On Self-Test (MPOST); Hardware Built-In Self-Test (HWBIST) for non-lockstep devices; functional safety compliant; designed for functional safety applications; documentation supporting ISO 26262 and IEC 61508 system design; system capability up to ASIL D and SIL 3; hardware integrity up to ASIL B and SIL 2; TÜV SÜD certified to ISO 26262 (up to ASIL B) and IEC 61508 (up to SIL 2).
Clock and System Control: Two internal 10MHz oscillators; on-chip crystal oscillator; 2 APLLs; BOR; redundant interrupt vector RAM; windowed watchdog timer module; clock failure detection circuit; Dual Clock Comparator (DCC); Live Firmware Update (LFU) for fast switchover from old to new firmware with or without power cycling; 1.2V core / 3.3V I/O design; internal VREG for 1.2V generation; brownout reset (BOR) circuit.
Package Options: Lead-free green packages — 256-ball nFBGA [ZEJ suffix], 13mm × 13mm / 0.8mm pitch; 176-pin PowerPAD HLQFP [PTP suffix], 26mm × 26mm / 0.5mm pitch; 169-ball nFBGA [NMR suffix], 9mm × 9mm / 0.65mm pitch; 100-pin PowerPAD HTQFP [PZP suffix], 16mm × 16mm / 0.5mm pitch.
Temperature: Ambient temperature T<sub>A</sub> = −40°C to 125°C (industrial and automotive grade qualified).