LP2995MR/NOPB

The LP2995 linear regulator is designed to meet the JEDEC SSTL-2 and SSTL-3 specifications for termination of DDR-SDRAM. The device contains a high-speed operational amplifier to provide excellent response to load transients. The output stage prevents shoot through while delivering 1.5A continuous current and transient peaks up to 3A in the application as required for DDR-SDRAM termination. The LP2995 also incorporates a VSENSE pin to provide superior load regulation and a VREF output as a reference for the chipset and DDR DIMMS. The LP2995 is a linear bus termination regulator designed to meet the JEDEC requirements of SSTL-2 and SSTL-3. The LP2995 is capable of sinking and sourcing current at the output VTT, regulating the voltage to equal VDDQ / 2. A buffered reference voltage that also tracks VDDQ / 2 is generated on the VREF pin for providing a global reference to the DDR-SDRAM and Northbridge Chipset. VTT is designed to track the VREF voltage with a tight tolerance over the entire current range while preventing shoot through on the output stage.

Applications

• DDR Termination Voltage
• SSTL-2
• SSTL-3

Key features

• Low Output Voltage Offset
• Works with +5v, +3.3v and 2.5v Rails
• Source and Sink Current
• Low External Component Count
• No External Resistors Required
• Linear Topology
• Available in SOIC-8, SO PowerPAD-8 or WQFN-16 Packages
• Low Cost and Easy to Use