LPC4330FET100,551

The LPC4350/30/20/10 are ARM Cortex-M4 microcontrollers for embedded applications, featuring one ARM Cortex-M0 coprocessor, up to 264 kB SRAM, advanced configurable peripherals (such as the State Configurable Timer (SCT) and Serial GPIO (SGPIO) interface), two high-speed USB controllers, Ethernet, LCD, one external memory controller, and multiple digital and analog peripherals. The LPC4350/30/20/10 series operates at CPU frequencies up to 204 MHz. The ARM Cortex-M4 is a next-generation 32-bit microcontroller core offering low power consumption, ease of debug, ease of integration, and numerous other system-enhancement advantages. The ARM Cortex-M4 core CPU employs a 3-stage pipeline and Harvard architecture with separate local instruction and data buses plus a third bus for system peripherals, and also includes an internal prefetch unit supporting speculative branch operations. The ARM Cortex-M4 supports single-cycle DSP and SIMD instructions. The core integrates a hardware floating-point unit. The ARM Cortex-M0 coprocessor is a highly energy-efficient 32-bit core that is easy to use and delivers outstanding performance, with code and toolchain compatibility with the Cortex-M4. As a replacement for existing 8/16-bit microprocessors, the Cortex-M0 coprocessor delivers performance up to 204 MHz with a simple instruction set and reduced code size. This datasheet describes revision "A" of the LPC4350/30/20/10 devices. The following updates have been made compared to previous revisions: • Operating frequency increased to 204 MHz. • C_CAN1 added. • Pin multiplexing expanded to 9 levels. • GPIO updated. • Pin description updated.

Applications

• Motor control
• Embedded audio applications
• Power management
• Industrial automation
• White goods
• Electronic metering
• RFID readers

Key features

• Cortex-M4 processor core operating frequency up to 204 MHz
• ARM Cortex-M4 with built-in MPU, supporting 8 regions
• ARM Cortex-M4 with built-in NVIC
• Integrated hardware floating-point unit
• NMI input
• JTAG and SWD support with 8 breakpoints and 4 watchpoints
• ETM and ETB support
• System tick timer
• ARM Cortex-M0 co-processor to offload the ARM Cortex-M4 main application processor, operating frequency up to 204 MHz
• Cortex-M0 co-processor supports JTAG, SWD, and built-in NVIC
• Up to 264 kB SRAM for code and data
• Multiple SRAM banks with independent bus access; 2 SRAM banks support independent power-down mode
• 64 kB ROM with boot code and on-chip software drivers
• 128-bit general-purpose OTP memory
• Integrated SGPIO interface
• Integrated SCT subsystem on AHB
• GIMA allows cross-connection of multiple inputs and outputs to event-driven peripherals (e.g., timers, SCT, and ADC0/1)
• Integrated quad-channel SPIFI with 4 channels, throughput up to 40 Mb/s
• Integrated 10/100T Ethernet MAC with RMII and MII interfaces and DMA support, enabling high throughput at low CPU load; supports IEEE 1588 timestamping / advanced timestamping (IEEE 1588-2008 v2)
• Integrated 1 high-speed USB 2.0 host/device/OTG interface with DMA support and on-chip high-speed PHY
• Integrated 1 high-speed USB 2.0 host/device interface with DMA support, on-chip full-speed PHY, and ULPI interface for external high-speed PHY
• ROM USB stack with USB electrical test software
• Integrated 1× 550 UART with DMA support and full modem interface
• Integrated 3× 550 USARTs with DMA and synchronous mode support, 1 ISO7816-compliant smart card interface, and 1 USART with IrDA interface
• Integrated 2× C_CAN 2.0B controllers, each with one channel
• Integrated 2× SSP controllers with FIFO and multi-protocol support; both support DMA
• Integrated 1× SPI controller
• Integrated ultra-fast-mode Plus I2C bus interface with monitor mode and open-drain I/O pins compliant with the full I2C bus specification, supporting data rates up to 1 Mbit/s
• Integrated standard I2C bus interface with monitor mode and standard I/O pins
• Integrated 2× I2S interfaces, each with DMA support and 1 input and 1 output
• Integrated EMC supporting external SRAM, ROM, NOR flash, and SDRAM devices
• LCD controller with DMA support, programmable display resolution up to 1024 H × 768 V; supports monochrome and color STN panels and TFT color panels; supports 1/2/4/8 bpp CLUT and 16/24-bit direct pixel mapping
• Integrated SD/MMC card interface
• Integrated 8-channel GPDMA controller with access to all memory on AHB and all DMA-capable AHB slave memory
• Up to 164 GPIO pins with configurable pull-up/pull-down resistors and open-drain mode
• GPIO registers on AHB for fast access; GPIO ports support DMA
• Up to 8 GPIO pins selectable from all GPIO pins as edge- and level-sensitive interrupt sources
• Integrated 2× GPIO grouped interrupt modules supporting programmable pattern-based interrupts from a set of GPIO pin input states
• Integrated 4× general-purpose timer/counters with capture and match
• Integrated 1× motor control PWM for three-phase motor control
• Integrated 1× QEI
• Integrated repetitive interrupt timer (RI timer)
• Integrated WWDT
• Dedicated power domain with ultra-low-power RTC, 256-byte battery-backed backup registers, alarm timer support, and battery power capability
• Integrated 1× 10-bit DAC with DMA support, conversion rate up to 400 kSamples/s
• Integrated 2× 10-bit ADCs with DMA support, conversion rate up to 400 kSamples/s; ADC inputs shared between both ADCs
• Integrated AES engine, programmable via on-chip API
• 2× 128-bit secure OTP memory for AES key storage and customer use
• Per-device unique ID
• Crystal oscillator operating frequency range: 1 MHz to 25 MHz
• Integrated 12 MHz IRC oscillator with 1% accuracy over temperature and voltage
• Integrated ultra-low-power RTC crystal oscillator
• Integrated 3× PLLs enabling maximum CPU speed without high-frequency crystals; second PLL dedicated to high-speed USB; third PLL usable as audio PLL
• Clock output support
• 3.3 V (2.2 V to 3.6 V) single-supply operation with on-chip DC-DC converter for core and RTC power domain
• RTC power domain independently powered by 3 V battery
• Four low-power modes: Sleep, Deep Sleep, Power-down, and Deep Power-down
• Wake-up from Sleep mode via interrupt from multiple peripherals
• Wake-up from Deep Sleep, Power-down, and Deep Power-down modes via external interrupts and interrupts from battery-powered modules in the RTC power domain
• Brown-out detection with 4 independent thresholds for interrupt and forced reset
• POR
• Available in 256-pin, 180-pin, and 100-pin LBGA packages, and 208-pin, 144-pin, and 100-pin LQFP packages