LPC54S005JBD100E

The LPC54018JxM/LPC54S018JxM is a family of ARM Cortex-M4 based microcontrollers for embedded applications featuring a rich peripheral set with very low power consumption and enhanced debug features. The ARM Cortex-M4 is a 32-bit core that offers system enhancements such as low power consumption, enhanced debug features, and a high level of support block integration. The ARM Cortex-M4 CPU incorporates a 3-stage pipeline, uses a Harvard architecture with separate local instruction and data buses as well as a third bus for peripherals, and includes an internal prefetch unit that supports speculative branching. The ARM Cortex-M4 supports single-cycle digital signal processing and SIMD instructions. A hardware floating-point processor is integrated into the core. The LPC54018JxM/LPC54S018JxM family includes 4 MB of on-chip Quad SPI Serial Flash (connected on SPIFI interface), 360 KB of on-chip SRAM, one high-speed and one full-speed USB host and device controller, Ethernet AVB, LCD controller, Smart Card Interfaces, SD/MMC, CAN FD, an External Memory Controller (EMC), a DMIC subsystem with PDM microphone interface and Π|²S, five general-purpose timers, SCTimer/PWM, RTC/alarm timer, Multi-Rate Timer (MRT), a Windowed Watchdog Timer (WWDT), ten flexible serial communication peripherals (USART, SPI, I2S, I2C interface), Secure Hash Algorithm (SHA), AES-256 engine, Physical Unclonable Function (PUF), secure boot features, 12-bit 5.0 Msamples/sec ADC, and a temperature sensor.

Key features

• ARM Cortex-M4 core (version r0p1):
• ARM Cortex-M4 processor, running at a frequency of up to 180 MHz.
• Floating Point Unit (FPU) and Memory Protection Unit (MPU).
• ARM Cortex-M4 built-in Nested Vectored Interrupt Controller (NVIC).
• Non-maskable Interrupt (NMI) input with a selection of sources.
• Serial Wire Debug (SWD) with six instruction breakpoints, two literal comparators, and four watch points. Includes Serial Wire Output and ETM Trace for enhanced debug capabilities, and a debug timestamp counter.
• System tick timer.
• On-chip memory:
• Up to 4 MB of on-chip Quad SPI Serial Flash (connected on SPIFI interface).
• Up to 360 KB total SRAM consisting of 160 KB contiguous main SRAM and an additional 192 KB SRAM on the I&D buses. 8 KB of SRAM bank intended for USB traffic.
• General-purpose One-Time Programmable (OTP) memory for user application specific data and for AES keys.
• ROM API support:
• In-Application Programming (IAP) and In-System Programming (ISP).
• ROM-based USB drivers (HID, CDC, MSC, and DFU).
• Supports serial interface booting (UART, I2C, SPI) from an application processor, automated booting from NOR flash (SPI, quad SPIFI, 8/16/32-bit external parallel flash), and USB booting (full-speed, high-speed).
• FRO API for selecting FRO output frequency.
• OTP API for programming OTP memory.
• Random Number Generator (RNG) API.
• RSA API calls (LPC54S018Jx only).
• Execute in place (XIP) from internal serial flash (in quad, dual SPIFI mode or single-bit SPI mode), and parallel NOR flash.
• Secure Boot features on LPC54S018Jx devices:
• Supports boot image authentication using RSASSA-PKCS1-v1_5 signature verification with 2048-bit public keys (2048-bit modulus, 32-bit exponent).
• Supports Root of Trust (RoT) establishment by comparing the SHA-256 hash digest of the RoT public key with OTP memory contents.
• Supports secure anti-rollback of images through revocation of image key certificate. Supports up to 8 revocations through OTP fuses.
• Supports boot of AES-GCM encrypted images with a 128-bit symmetric key stored in OTP memory or a 256-bit symmetric key stored using on-chip SRAM PUF.
• Secure Authentication Only Boot. Enforce booting of RSA-2048 signed images only.
• Encrypted Image Boot. Enforce booting of AES-GCM encrypted images only.
• Enhanced Image Boot. Enforce booting of encrypted then signed images only.
• Security features:
• AES-256 encryption/decryption engine with keys stored in polyfuse OTP (LPC54S018Jx only).
• Random number generator can be used to create keys with DMA support.
• Secure Hash Algorithm (SHA1/SHA2) module supports boot with dedicated DMA controller.
• Physical Unclonable Function (PUF) root key using dedicated SRAM for silicon fingerprint. PUF can generate, store, and reconstruct key sizes from 64 to 4096 bits (LPC54S018Jx only).
• Serial interfaces:
• Flexcomm Interface contains up to 11 serial peripherals. Each Flexcomm Interface (except flexcomm 10, which is dedicated for SPI) can be selected by software to be a USART, SPI, or I2C interface. Two Flexcomm Interfaces also include an I2S interface. Each Flexcomm Interface includes a FIFO that supports USART, SPI, and I2S if supported by that Flexcomm Interface. A variety of clocking options are available to each Flexcomm Interface and include a shared fractional baud-rate generator.
• I2C-bus interfaces support Fast-mode and Fast-mode Plus with data rates of up to 1Mbit/s and with multiple address recognition and monitor mode. Two sets of true I2C pads also support High Speed Mode (3.4 Mbit/s) as a slave.
• Two ISO 7816 Smart Card Interfaces with DMA support.
• USB 2.0 high-speed host/device controller with on-chip high-speed PHY.
• USB 2.0 full-speed host/device controller with on-chip PHY and dedicated