LPC5516JEV59E

The LPC55S1x/LPC551x is an Arm Cortex-M33 based microcontroller for embedded applications. These devices include CASPER Crypto engine, up to 256 KB on-chip flash, up to 96 KB of on-chip SRAM, PRINCE module for on-the-fly flash encryption/decryption, Code Watchdog, high-speed/full-speed USB host and device interface with crystal-less operation for full-speed, CAN FD, five general-purpose timers, one SCTimer/PWM, one RTC/alarm timer, one 24-bit Multi-Rate Timer (MRT), a Windowed Watchdog Timer (WWDT), nine flexible serial communication peripherals (which can be configured as a USART, SPI, high speed SPI, I2C, or I2S interface), Programmable Logic Unit (PLU), one 16-bit 2.0 Msamples/sec ADC capable of simultaneous conversions, comparator, and temperature sensor. The Arm Cortex-M33 provides a security foundation, offering isolation to protect valuable IP and data with TrustZone technology. It simplifies the design and software development of digital signal control systems with the integrated digital signal processing (DSP) instructions. To support security requirements, the LPC55S1x/LPC551x also offers support for secure boot, HASH, AES, RSA, UUID, DICE, dynamic encrypt and decrypt, debug authentication, and TBSA compliance.

Key features

• Arm Cortex-M33 core (r0p4):
• Running at a frequency of up to 150 MHz.
• Integrated digital signal processing (DSP) instructions.
• TrustZone, Floating Point Unit (FPU) and Memory Protection Unit (MPU).
• Arm Cortex M33 built-in Nested Vectored Interrupt Controller (NVIC).
• Non-maskable Interrupt (NMI) input with a selection of sources.
• Serial Wire Debug with eight breakpoints and four watch points. Includes Serial Wire Output for enhanced debug capabilities.
• System tick timer.
• CASPER Crypto co-processor is provided to enable hardware acceleration for various functions required for certain asymmetric cryptographic algorithms, such as, Elliptic Curve Cryptography (ECC).
• On-chip memory:
• Up to 256 KB on-chip flash program memory with flash accelerator and 512 byte page erase and write.
• Up to 96 KB total SRAM consisting of 16 KB SRAM on Code Bus, 64 KB SRAM on System Bus (64 KB is contiguous), and additional 16 KB USB SRAM on System Bus which can be used by the USB interface or for general purpose use.
• PRINCE module for real-time encryption of data being written to on-chip flash and decryption of encrypted flash data during read to allow asset protection, such as securing application code, and enabling secure flash update.
• On-chip ROM bootloader supports:
• Booting of images from on-chip flash
• Supports CRC32 image integrity checking.
• Supports flash programming through In System Programming (ISP) commands over following interfaces: USB0/1 interfaces using HID Class device, UART interface (Flexcomm 0) with auto baud, SPI slave interfaces (Flexcomm 3 or 8) using mode 3 (CPOL = 1 and CPHA = 1), and I2C slave interface (Flexcomm 1)
• ROM API functions: Flash programming API, Power control API, and Secure firmware update API using NXP Secure Boot file format, version 2.0 (SB2 files).
• Supports booting of images from PRINCE encrypted flash regions.
• Support NXP Debug Authentication Protocol version 1.0 (RSA-2048) and 1.1 (RSA-4096).
• Supports setting a sealed part to Fault Analysis mode through Debug authentication.
• Uses RSASSA-PKCS1-v1_5 signature of SHA256 digest as cryptographic signature verification.
• Supports RSA-2048 bit public keys (2048 bit modulus, 32-bit exponent).
• Supports RSA-4096 bit public keys (4096 bit modulus, 32-bit exponent).
• Uses X509 certificate format to validate image public keys.
• Supports up to four revocable Root of Trust (RoT) or Certificate Authority keys, Root of Trust establishment by storing the SHA-256 hash digest of the hashes of four RoT public keys in protected flash region (PFR).
• Supports anti-rollback feature using image key revocation and supports up to 16 Image key certificates revocations using Serial Number field in X509 certificate.
• Supports Device Identifier Composition Engine (DICE) Specification (version Family 2.0, Level 00 Revision 69) specified by Trusted Computing Group.
• Serial interfaces:
• Flexcomm Interface contains up to nine serial peripherals (Flexcomm Interface 0 - 7 and Flexcomm Interface 8). Each Flexcomm Interface (except flexcomm 8, which is dedicated for high-speed SPI) can be selected by software to be a USART, SPI, I2C, and I2S interface. Each Flexcomm Interface includes a FIFO that supports USART, SPI, and I2S. A variety of clocking options are available to each Flexcomm Interface, including a shared fractional baud-rate generator, and time-out feature. Flexcomm interfaces 0 to 5 each provide one channel pair of I2S and Flexcomm interfaces 6 to 7 each provide four channel pairs of I2S.
• I2C-bus interfaces support Fast-mode and Fast-mode Plus with data rates of up to 1Mbit/s and with multiple address recognition and monitor mode. Two sets of true I2C pads also support high-speed Mode (3.4 Mbit/s) as a slave.
• USB 2.0 full speed host/device controller with on-chip PHY and dedicated DMA controller supporting crystal-less operation in device mode using software library example in technical