MC9S08AW48CFDE

Key features

• 40-MHz HCS08 CPU
• 20-MHz internal bus frequency
• HC08 instruction set with BGND instruction added
• Background debug system supports single breakpoint during in-circuit debugging (two additional breakpoints in on-chip debug mode)
• Debug mode includes 2 comparators and 9 trigger modes
• 8 FIFOs for storing flow control addresses and event data
• Debug mode supports tagged and force breakpoints
• Up to 32 interrupt/reset sources
• Up to 16KB on-chip in-circuit programmable FLASH memory with block protection and security options
• Up to 1KB on-chip RAM
• Clock source options include crystal, oscillator, external clock, or precision internal integrated clock with NVM trimming capability
• Optional watchdog (COP) reset using independent internal clock source or bus clock
• Low-voltage detect reset or interrupt
• Illegal opcode detect reset
• Illegal address detect reset
• Wait mode and two stop modes
• ADC — 8-channel, 10-bit ADC with automatic compare function
• SCI — Two serial communication interface modules with optional 13-bit break character communication mode
• SPI — Serial peripheral interface module
• IIC — Inter-integrated circuit bus module; transfer speed up to 100kbps at maximum bus load; reduced load allows higher baud rates
• Timers — Three 16-bit timer/PWM (TPM) modules — two 2-channel and one 4-channel; each timer channel supports selectable input capture, output compare, and PWM; each timer channel configurable for edge-aligned operation; each TPM can generate center-aligned PWM (CPWM) on all its channels
• KBI — 7-pin keyboard interrupt module
• Up to 38 general-purpose I/O pins
• Input: software-selectable pull-up resistor per port
• Output: software-selectable slew rate control per port
• Output: software-selectable drive strength per port
• Master reset pin and power-on reset (POR)
• RESET, IRQ, and BKGD/MS pins internally pulled up to reduce customer system cost
• 48-pin QFN
• 44-pin LQFP
• 42-pin SDIP
• 32-pin LQFP