MC9S08LL36CLH

Key features

• 8-Bit HCS08 Central Processor Unit (CPU) – Up to 20-MHz CPU at 3.6V to 1.8V across temperature range of -40℃ to 85℃ – HC08 instruction set with added BGND instruction – Support for up to 32 interrupt/reset sources
• On-Chip Memory – Dual Array FLASH read/program/erase over full operating voltage and temperature Random-access memory (RAM) – Security circuitry to prevent unauthorized access to RAM and FLASH contents
• Power-Saving Modes – Two low power stop modes – Reduced power wait mode – Low power run and wait modes allow peripherals to run while voltage regulator is in standby – Peripheral clock gating register can disable clocks to unused modules, thereby reducing currents. – Very low power external oscillator that can be used in stop2 or stop3 modes to provide accurate clock source to real time counter – 6 usec typical wake up time from stop3 mode
• Clock Source Options – Oscillator (XOSC) — Loop-control Pierce oscillator; Crystal or ceramic resonator range of 31.25 kHz to 38.4 kHz or 1 MHz to 16 MHz – Internal Clock Source (ICS) — Internal clock source module containing a frequency-locked-loop (FLL) controlled by internal or external reference; precision trimming of internal reference allows 0.2% resolution and 2% deviation over temperature and voltage; supports bus frequencies from 1MHz to 10 MHz.
• System Protection Watchdog computer operating properly (COP) reset with option to run from dedicated 1-kHz internal clock source or bus clock – Low-Voltage Warning with interrupt – Low-Voltage Detection with reset or interrupt – Illegal opcode and illegal address detection with reset – Flash block protection
• Development Support – Single-wire background debug interface Breakpoint capability to allow single breakpoint setting during in-circuit debugging (plus two more breakpoints in on-chip debug module)
• On-chip in-circuit emulator (ICE) debug module containing three comparators and nine trigger modes. Eight deep FIFO for storing change-of-flow addresses and event-only data. Debug module supports both tag and force breakpoints
• Peripherals – LCD — 4x28 or 8x24 LCD driver with internal charge pump and option to provide an internally regulated LCD reference that can be trimmed for contrast control. – ADC — 8-channel, 12-bit resolution; 2.5 μs conversion time; automatic compare function; temperature sensor; internal bandgap reference channel; operation in stop3; fully functional from 3.6V to 1.8V – ACMP — Analog comparator with selectable interrupt on rising, falling, or either edge of comparator output; compare option to fixed internal bandgap reference voltage; outputs can be optionally routed to TPM module; operation in stop3 SCI — Full duplex non-return to zero (NRZ); LIN master extended break generation; LIN slave extended break detection; wake up on active edge SPI— Full-duplex or single-wire bidirectional; Double-buffered transmit and receive; Master or Slave mode; MSB-first or LSB-first shifting – IIC — IIC with up to 100 kbps with maximum bus loading; Multi-master operation; Programmable slave address; Interrupt driven byte-by-byte data transfer; supports broadcast mode and 10-bit addressing TPMx — Two 2-channel (TPM1 and TPM2); Selectable input capture, output compare, or buffered edge- or center-aligned PWM on each channel; – TOD— (Time Of Day) 8-bit quarter second counter with match register; External clock source for precise time base, time-of-day, calendar or task scheduling functions; Free running on-chip low power oscillator (1 kHz) for cyclic wake-up without external components.
• 38 GPIOs, 2 output-only pins – 8 KBI interrupts with selectable polarity Hysteresis and configurable pull up device on all input pins; Configurable slew rate and drive strength on all output pins.
• Package Options – 64-LQFP, 48-LQFP and 48-QFN