PIC18F26Q24-I/SO

The PIC18-Q24 microcontroller family features 28/40/44/48-pin devices for sensor interface, real-time control, and communication applications. The family showcases Multi-Voltage I/O (MvIO) interfaces, where multiple I/O pins are powered by an optional VDD pin, allowing these pins to operate in a different voltage domain from the rest of the microcontroller. The family also features a 10-bit ADC with Computation (ADCC) capable of 300 ksps, and an 8-bit Signal Routing Port module that interconnects digital peripherals without using external pins. In addition, the PIC18-Q24 microcontroller family provides enhanced code protection features to strengthen the security and protection of user firmware and data. These enhanced code protection features include the ability to disable programming and debugging interfaces to achieve one-time device programmability and effectively block any unauthorized communication attempts with the device through the ICSPm interface. Additional features include a Vectored Interrupt Controller with fixed latency for interrupt handling, a system bus arbiter, Direct Memory Access (DMA) capability, UART supporting asynchronous, DMX-512, Digital Addressable Lighting Interface (DALI), and Local Interconnect Network (LIN) protocols, SPI, and I²C. The family also includes memory features such as Memory Access Partition (MAP) and Device Information Area (DIA), which stores factory-calibrated values to help improve temperature sensor accuracy.

Applications

• Sensor interface
• Real-time control
• Communication

Key features

• C compiler-optimized RISC architecture; operating speed: DC – 64 MHz clock input, minimum instruction cycle 62.5 ns
• Multi-Voltage I/O (MVIO): enables operation in voltage domains different from the normal MCU operating voltage, provides multiple I/O pins powered by the VDDIO2 voltage domain, VDDIO2 domain features dedicated low-voltage detection circuitry and interrupts, MVIO pins support voltage range of 1.62V to 5.5V
• Four Direct Memory Access (DMA) controllers: data transfer from program Flash, data EEPROM, or SFR/GPR space to SFR/GPR space, user-programmable source and destination sizes, hardware- and software-triggered data transfers
• Vectored interrupt capability: selectable high/low priority, fixed three-instruction-cycle interrupt latency, programmable vector table base address, backward compatible with legacy interrupt capability
• 128-level deep hardware stack
• Low-current Power-on Reset (POR)
• Configurable Power-up Timer (PWRT)
• Brown-out Reset (BOR)
• Low-Power Brown-out Reset (LPBOR) option
• Windowed Watchdog Timer (WWDT): watchdog reset on excessively long or short intervals between watchdog clear events, variable prescaler selection, variable window size selection