PIC18F45K42-E/PT

The PIC18(L)F2X/4X/5XK42 microcontroller family is available in 28/40/44/48-pin devices. This family features a 12-bit ADC with Computation (ADC²) automating Capacitive Voltage Divider (CVD) techniques for advanced touch sensing, averaging, filtering, oversampling and threshold comparison. Additionally, Vectored Interrupt Controller with fixed latency for handling interrupts, System Bus Arbiter, Direct Memory Access capabilities, UART with support for Asynchronous, DMX, DALI and LIN protocols, SPI, I²C, memory features like Memory Access Partition (MAP) to support customers in data protection and bootloader applications, Device Information Area (DIA) which stores factory calibration values to help improve temperature sensor accuracy.

Key features

• C Compiler Optimized RISC Architecture
• Operating Speed:
• Up to 64 MHz clock input
• 62.5 ns minimum instruction cycle
• Two Direct Memory Access (DMA) Controllers:
• Data transfers to SFR/GPR spaces from either Program Flash Memory, Data EEPROM or SFR/GPR spaces
• User programmable source and destination sizes
• Hardware and software triggered data transfers
• Vectored Interrupt Capability:
• Selectable high/low priority
• Fixed Interrupt latency
• Programmable vector table base address
• 31-Level Deep Hardware Stack
• Low-Current Power-on Reset (POR)
• Configurable Power-up Timer (PWRTE)
• Brown-Out Reset (BOR)
• Low-Power BOR (LPBOR) Option
• Windowed Watchdog Timer (WWDT):
• Variable prescaler selection
• Variable window size selection
• Configurable in hardware or software
• Programmable Code Protection:
• Configurable Boot and App region sizes
• Up to 128 KB Flash Program Memory
• Up to 8 KB Data SRAM Memory
• Up to 1 KB Data EEPROM
• Memory Access Partition (MAP):
• Bootloader write-protect
• Configurable partition
• Device Information Area (DIA) Stores:
• Temp sensor factory calibrated data
• Fixed Voltage Reference
• Device ID
• Operating Voltage Range:
• 1.8V to 3.6V (PIC18LF2X/4X/5XK42)
• 2.3V to 5.5V (PIC18F2X/4X/5XK42)
• Temperature Range:
• Industrial: -40℃ to 85℃
• Extended: -40℃ to 125℃
• DOZE mode: Ability to run CPU core slower than the system clock
• IDLE mode: Ability to halt CPU core while internal peripherals continue operating
• Sleep mode: Lowest power consumption
• Peripheral Module Disable (PMD): Ability to disable peripherals to minimize power consumption
• Sleep mode: 50 nA @ 1.8V, typical
• Watchdog Timer: 500 nA @ 1.8V, typical
• Secondary Oscillator: 500 nA @ 32 kHz
• Operating Current:
• 8 uA @ 32 kHz, 1.8V, typical
• 32 uA/MHz @ 1.8V, typical
• Three 8-Bit Timers (TMR2/4/6) with Hardware Limit Timer (HLT)
• Four 16-Bit Timers (TMR0/1/3/5)
• Four Configurable Logic Cell (CLC): Integrated combinational and sequential logic
• Three Complementary Waveform Generators (CWGs):
• Rising and falling edge dead-band control
• Full-bridge, half-bridge, 1-channel drive
• Multiple signal sources
• Programmable dead band
• Fault-shutdown input
• Four 16-Bit Capture/Compare/16-Bit PWM (CCP) modules
• Four 10-bit Pulse Width Modulators (PWMs)
• Numerically Controlled Oscillator (NCO):
• Generates true linear frequency control and increased frequency resolution
• Input Clock: 0 Hz < fNCO < 64 MHz
• Resolution: fNCO/220
• DSM: Data Signal Modulator:
• Multiplex two carrier clocks, with glitch prevention feature
• Multiple sources for each carrier
• Programmable CRC with Memory Scan:
• Reliable data/program memory monitoring for fail-safe operation (e.g., Class B)
• Calculate CRC over any portion of Flash
• Two UART Modules:
• Asynchronous UART, RS-232, RS-485 compatible.
• One of the UART modules supports LIN master and slave, DMX mode, DALI gear and device protocols
• Automatic and user timed BREAK period generation
• DMA compatible
• Automatic checksums
• Programmable 1, 1.5, and 2 Stop bits
• Wake-up on BREAK reception
• One SPI module:
• Configurable length bytes
• Arbitrary length data packets
• Receive-without-transmit option
• Transmit-without-receive option
• Transfer byte counter
• Separate transmit and receive buffers with 2-byte FIFO and DMA capabilities
• Two I²C modules, SMBus, PMBus compatible:
• Dedicated address, transmit and receive buffers
• Bus collision detection with arbitration
• Bus time-out detection and handling
• I²C, SMBus 2.0 and SMBus 3.0, and 1.8V input level selections
• Multi-Master mode, including self-addressing
• Device I/O Port Features:
• 25 I/O pins (PIC18(L)F24/25/26/27K42)
• 36 I/O pins (PIC18(L)F45/46/47K42)
• 44 I/O pins (PIC18(L)F55/56/57K42)
• One input-only pin
• Individually programmable I/O direction, controlled current, open-drain, slew rate, weak pull-up control
• Interrupt-on-change
• Three external interrupt pins
• Peripheral Pin Select (PPS): Enables pin mapping of digital I/O
• Signal Measurement Timer (SMT): 24-bit timer/counter with prescaler
• Analog-to-Digital Converter with Computation (ADC2):
• 12-bit with up to 43 external channels
• Automated post-processing
• Automates math functions on input signals: averaging, filter calculations, oversampling and threshold comparison
• Operates in Sleep
• Temperature Sensor
• Internal connection to ADC
• Can be calibrated for improved accuracy
• Hardware Capacitive Voltage Divider (CVD):
• Automates touch sampling and reduces software size and CPU usage when touch or proximity sensing is required
• Adjustable sample and hold capacitor array
• Two guard ring output drives
• Two Comparators:
• Comparator Hysteresis enable
• Invert output