PIC18F45Q24-E/PT

The PIC18-Q24 microcontroller family offers 28/40/44/48-pin devices for sensor interface, real-time control, and communication applications. The family features a Multi-Voltage I/O (MVIO) interface, where the I/O of multiple pins is powered by an optional VDD pin, enabling these pins to operate in a different voltage domain from the rest of the microcontroller. The family also integrates a 10-bit ADC with Computation (ADCC) at up to 300 ksps, and an 8-bit Signal Routing Port module that interconnects digital peripherals without using external pins. Additionally, the PIC18-Q24 microcontroller family provides enhanced code protection features to strengthen the security and protection of user firmware and data. These enhanced code protection features include the ability to disable the programming and debugging interface for one-time device programming, effectively blocking any unauthorized communication attempts with the device via the ICSP interface. Additional features include a Fixed-Latency Vector Interrupt Controller for interrupt handling, a system bus arbiter, DMA capability, UART supporting asynchronous, DMX-512, DALI²P, and LIN protocols, SPI, and I²C. The family also includes memory features such as Memory Access Partition (MAP) and Device Information Area (DIA), the latter storing factory-calibrated values to help improve temperature sensor accuracy.

Key features

• RISC architecture optimized for C compilers
• Operating speed:
• DC – 64 MHz clock input
• Minimum instruction cycle 62.5 ns
• Multi-Voltage I/O (MVIO):
• Allows operation in voltage domains different from the normal MCU operating voltage
• Provides multiple I/O pins powered by the VDD102 voltage domain
• Dedicated low-voltage detect circuit and interrupt for the VDDIO2 domain
• MVIO pins support voltage range of 1.62V to 5.5V
• Four Direct Memory Access (DMA) controllers:
• Data transfer from program Flash, data EEPROM, or SFR/GPR space to SFR/GPR space
• User-programmable source and destination sizes
• Hardware and software triggered data transfers
• Vectored interrupt capability:
• Selectable high/low priority
• Fixed three-instruction-cycle interrupt latency
• Programmable vector table base address
• Backward compatible with previous interrupt capability
• 128-level deep hardware stack
• Low-current Power-on Reset (POR)
• Configurable Power-up Timer (PWRT)
• Brown-out Reset (BOR)
• Low-Power Brown-out Reset (LPBOR) option
• Windowed Watchdog Timer (WWDT):
• Watchdog Reset when interval between watchdog clear events is too long or too short
• Variable prescaler selection
• Variable window size selection