PIC18F65J94-I/PT

Key features

• Multiple Power Management Options for Extreme Power Reduction:
• VBAT allows for lowest power consumption on back-up battery (with or without RTCC)
• Deep Sleep allows near total power-down with the ability to wake-up on external triggers
• Sleep and Idle modes selectively shut down peripherals and/or core for substantial power reduction and fast wake-up
• Alternate Clock modes Allow On-the-Fly Switching to a Lower Clock Speed for Selective Power Reduction
• Extreme Low-Power Current Consumption for Deep Sleep:
• WDT: 650 nA @ 2V typical
• RTCC: 650 nA @ 32 kHz, 2V typical
• Deep Sleep current, 80 nA typical
• USB V2.0 Compliant
• Low Speed (1.5 Mb/s) and Full Speed (12 Mb/s)
• Supports Control, Interrupt, Isochronous and Bulk Transfers
• Supports up to 32 Endpoints (16 bidirectional)
• USB module can use Any RAM Location on the Device as USB Endpoint Buffers
• On-Chip USB Transceiver
• LCD Display Controller:
• Up to 60 segments by 8 commons
• Internal charge pump and low-power, internal resistor biasing
• Operation in Sleep mode
• Up to Four External Interrupt Sources
• Peripheral Pin Select Lite (PPS-Lite):
• Allows independent I/O mapping of many peripherals
• Four 16-Bit and Four 8-Bit Timers/Counters with Prescaler
• Seven Capture/Compare/PWM (CCP) modules
• Three Enhanced Capture/Compare/PWM (ECCP) modules:
• One, two or four PWM outputs
• Selectable polarity
• Programmable dead time
• Auto-shutdown and auto-restart
• Pulse steering control
• Hardware Real-Time Clock/Calendar (RTCC):
• Runs in Deep Sleep and VBAT modes
• Two Master Synchronous Serial Ports (MSSP) modules Featuring:
• 3-Wire/4-Wire SPI (all 4 modes)
• SPI Direct Memory Access (DMA) channel w/1024 byte count
• Two I2C modules Support Multi-Master/Slave mode and 7-Bit/10-Bit Addressing
• Four Enhanced Addressable USART modules:
• Support RS-485, RS-232 and LIN/J2602
• On-chip hardware encoder/decoder for IrDA
• Auto-wake-up on Auto-Baud Detect
• Digital Signal Modulator Provides On-Chip OOK, FSK and PSK Modulation for a Digital Signal Stream
• High-Current Sink/Source 18 mA/18 mA on all Digital I/O
• Configurable Open-Drain Outputs on ECCP/CCP/ USART/MSSP
• Extended Microcontroller mode Using 12, 16 or 20-Bit Addressing mode
• 10/12-Bit, 24-Channel Analog-to-Digital (A/D) Converter:
• Conversion rate of 500 ksps (10-bit), 200 kbps (12-bit)
• Conversion available during Sleep and Idle
• Three Rail-to-Rail Enhanced Analog Comparators with Programmable Input/Output Configuration
• On-Chip Programmable Voltage Reference
• Charge Time Measurement Unit (CTMU):
• Used for capacitive touch sensing, up to 24 channels
• Time measurement down to 1 ns resolution
• CTMU temperature sensing
• High-Precision PLL for USB
• Two External Clock modes, Up to 64 MHz (16 MIPS)
• Internal 31 kHz Oscillator
• High-Precision Internal Oscillator with Clock Recovery from SOSC to Achieve 0.15% Precision, 31 kHz to 8 MHz or 64 MHz w/PLL, ±0.15% Typical, ±1.5% Max.
• Secondary Oscillator using Timer1 @ 32 kHz
• C Compiler Optimized Instruction Set Architecture
• Two Address Generation Units for Separate Read and Write Addressing of Data Memory
• Operating Voltage Range of 2.0V to 3.6V
• Two On-Chip Voltage Regulators (1.8V and 1.2V) for Regular and Extreme Low-Power Operation
• 20,000 Erase/Write Cycle Endurance Flash Program Memory, Typical
• Flash Data Retention: 10 Years Minimum
• Self-Programmable under Software Control
• Two Configurable Reference Clock Outputs (REFO1 and REFO2)
• In-Circuit Serial Programming (ICSP)
• Fail-Safe Clock Monitor Operation:
• Detects clock failure and switches to on-chip, low-power RC oscillator
• Power-on Reset (POR), Power-up Timer (PWRT) and Oscillator Start-up Timer (OST)
• Brown-out Reset (BOR) with Operation Below VBOR, with Regulator Enabled
• High/Low-Voltage Detect (HLVD)
• Flexible Watchdog Timer (WDT) with its Own RC Oscillator for Reliable Operation
• Standard and Ultra Low-Power Watchdog Timers (WDT) for Reliable Operation in Standard and Deep Sleep modes