PIC24FJ128GA202-I/MM

Key features

• AES Engine with 128, 192 or 256-Bit Key
• Supports ECB, CBC, OFB, CTR and CFB128 modes
• DES/Triple DES (TDES) Engine: Supports 2-Key and 3-Key EDE or DED TDES
• Supports up to Three Unique Keys for TDES
• Programmatically Secure
• Pseudorandom Number Generator
• True Random Number Generator
• Non-Readable, On-Chip, OTP Key Storages
• Multiple Power Management Options for Extreme Power Reduction:
• VBAT allows the device to transition to a backup battery for the lowest power consumption with RTCC
• Deep Sleep allows near total power-down with the ability to wake-up on internal or external triggers
• Sleep and Idle modes selectively shut down peripherals and/or core for substantial power reduction and fast wake-up
• Doze mode allows CPU to run at a lower clock speed than peripherals
• Alternate Clock modes allow On-the-Fly Switching to a Lower Clock Speed for Selective Power Reduction
• Extreme Low-Power Current Consumption for Deep Sleep:
• WDT: 270 nA @3.3V typical
• RTCC: 400 nA @ 32 kHz, 3.3V typical
• Deep Sleep current: 40 nA, 3.3V typical
• 10/12-Bit, 13-Channel Analog-to-Digital (A/D) Converter:
• Conversion rate of 500 ksps (10-bit), 200 ksps (12-bit)
• Conversion available during Sleep and Idle
• Three Rail-to-Rail, Enhanced Analog Comparators with Programmable Input/Output Configuration
• Three On-Chip Programmable Voltage References
• Charge Time Measurement Unit (CTMU):
• Used for capacitive touch sensing, up to 13 channels
• Time measurement down to 100 ps resolution
• Operation in Sleep mode
• Up to Five External Interrupt Sources
• Peripheral Pin Select (PPS); Allows Independent I/O Mapping of Many Peripherals
• Five 16-Bit Timers/Counters with Prescaler:
• Can be paired as 32-bit timers/counters
• Six-Channel DMA supports All Peripheral modules:
• Minimizes CPU overhead and increases data throughput
• Six Input Capture modules, Each with a Dedicated 16-Bit Timer
• Six Output Compare/PWM modules, Each with a Dedicated 16-Bit Timer
• Enhanced Parallel Master/Slave Port (EPMP/EPSP)
• Hardware Real-Time Clock/Calendar (RTCC):
• Runs in Sleep, Deep Sleep and VBAT modes
• Three 3-Wire/4-Wire SPI modules:
• Support four Frame modes
• Variable FIFO buffer
• I2S mode
• Variable width from 2-bit to 32-bit
• Two I²C modules Support Multi-Master/Slave mode and 7-Bit/10-Bit Addressing
• Four UART modules:
• Support RS-485, RS-232 and LIN/J2602
• On-chip hardware encoder/decoder for IrDA
• Smart Card ISO 7816 support on UART1 and UART2 only:
• T=0 protocol with automatic error handling
• T=1 protocol
• Dedicated Guard Time Counter (GTC)
• Dedicated Waiting Time Counter (WTC)
• Auto-wake-up on Auto-Baud Detect (ABD)
• 4-level deep FIFO buffer
• Programmable 32-Bit Cyclic Redundancy Check (CRC) Generator
• Digital Signal Modulator provides On-Chip FSK and PSK Modulation for a Digital Signal Stream
• High-Current Sink/Source (18 mA/18 mA) on All I/O Pins
• Configurable Open-Drain Outputs on Digital I/O Pins
• 5.5V Tolerant Inputs on Most Pins
• Modified Harvard Architecture
• Up to 16 MIPS Operation @32 MHz
• 8 MHz Internal Oscillator:
• 96 MHz PLL option
• Multiple clock divide options
• Run-time self-calibration capability for maintaining better than ±0.20% accuracy
• Fast start-up
• 17-Bit x 17-Bit Single-Cycle Hardware Fractional/Integer Multiplier
• 32-Bit by 16-Bit Hardware Divider
• 16x16-Bit Working Register Array
• C Compiler Optimized Instruction Set Architecture (ISA)
• Two Address Generation Units (AGUs) for Separate Read and Write Addressing of Data Memory
• Supply Voltage Range of 2.0V to 3.6V
• Two On-Chip Voltage Regulators (1.8V and 1.2V) for Regular and Extreme Low-Power Operation
• 20,000 Erase/Write Cycle Endurance Flash Program Memory, Typical
• Flash Data Retention: 20 Years Minimum
• Self-Programmable under Software Control
• Programmable Reference Clock Output
• In-Circuit Serial Programming™ (ICSP™) and In-Circuit Emulation (ICE) via 2 Pins
• JTAG Programming and Boundary Scan Support
• Fail-Safe Clock Monitor (FSCM) Operation:
• Detects clock failure and switches to on-chip, Low-Power RC Oscillator (LPRC)
• Power-on Reset (POR), Power-up Timer (PWRT) and Oscillator Start-up Timer (OST)
• Separate Brown-out Reset (BOR) and Deep Sleep Brown-out Reset (DSBOR) Circuits
• Programmable High/Low-Voltage Detect (HLVD)
• Flexible Watchdog Timer (WDT) with its Own RC Oscillator for Reliable Operation
• Standard and Ultra Low-Power Watchdog Timers (ULPWs) for Reliable Operation in Standard and Deep Sleep modes