PIC24FJ64GA702-I/SO

Key features

• Modified Harvard Architecture
• Up to 16 MIPS Operation @ 32 MHz
• 8 MHz Fast RC Internal Oscillator:
• 96 MHz PLL option
• Multiple clock divide options
• Fast start-up
• 17-Bit x 17-Bit Single-Cycle Hardware Fractional/Integer Multiplier
• 32-Bit by 16-Bit Hardware Divider
• 16-Bit x 16-Bit Working Register Array
• C Compiler Optimized Instruction Set Architecture
• Two Address Generation Units for Separate Read and Write Addressing of Data Memory
• Six-Channel DMA Controller
• Up to 14-Channel, Software-Selectable, 10/12-Bit Analog-to-Digital Converter:
• 12-bit, 200K samples/second conversion rate (single Sample-and-Hold)
• Sleep mode operation
• Charge pump for operating at lower AVDD
• Band gap reference input feature
• Windowed threshold compare feature
• Auto-scan feature
• Three Analog Comparators with Input Multiplexing:
• Programmable reference voltage for comparators
• LVD Interrupt Above/Below Programmable VLVD Level
• Charge Time Measurement Unit (CTMU):
• Allows measurement of capacitance and time
• Operational in Sleep
• Sleep and Idle modes Selectively Shut Down Peripherals and/or Core for Substantial Power Reduction and Fast Wake-up
• Doze mode allows CPU to Run at a Lower Clock Speed than Peripherals
• Alternate Clock modes allow On-the-Fly Switching to a Lower Clock Speed for Selective Power Reduction
• Supply Voltage Range of 2.0V to 3.6V
• Dual Voltage Regulators:
• 1.8V core regulator
• 1.2V regulator for Retention Sleep mode
• Operating Ambient Temperature Range of -40°C to +125°C
• ECC Flash Memory (256 Kbytes):
• Single Error Correction (SEC)
• Double Error Detection (DED)
• 10,000 erase/write cycle endurance, typical
• Data retention: 20 years minimum
• Self-programmable under software control
• 16-Kbyte SRAM
• Programmable Reference Clock Output
• In-Circuit Serial Programming (ICSP) and In-Circuit Emulation (ICE) via 2 Pins
• JTAG Boundary Scan Support
• Fail-Safe Clock Monitor Operation:
• Detects clock failure and switches to on-chip, Low-Power RC (LPRC) Oscillator
• Power-on Reset (POR), Brown-out Reset (BOR) and Oscillator Start-up Timer (OST)
• Programmable Low-Voltage Detect (LVD)
• Flexible Watchdog Timer (WDT) with its Own RC Oscillator for Reliable Operation
• AEC-Q100 REVG (Grade 1 -40°C to +125°C)
• Class B Safety Library, IEC 60730
• High-Current Sink/Source 18 mA/18 mA on All I/O Pins
• Independent, Low-Power 32 kHz Timer Oscillator
• Timer1: 16-Bit Timer/Counter with External Crystal Oscillator; Timer1 can Provide an A/D Trigger
• Timer2,3: 16-Bit Timer/Counter, can Create 32-Bit Timer; Timer3 can Provide an A/D Trigger
• Three Input Capture modules, Each with a 16-Bit Timer
• Three Output Compare/PWM modules, Each with a 16-Bit Timer
• Four MCCP modules, Each with a Dedicated 16/32-Bit Timer:
• One 6-output MCCP module
• Three 2-output MCCP modules
• Three Variable Widths, Synchronous Peripheral Interface (SPI) Ports on All Devices; Three Operation modes:
• Three-wire SPI (supports all four SPI modes)
• 8 by 16-bit or 8 by 8-bit FIFO
• I2S mode
• Two I²C Masters and Slaves w/Address Masking, and IPMI Support
• Two UART modules:
• LIN/J2602 bus support (auto-wake-up, Auto-Baud Detect (ABD), Break character support)
• RS-232 and RS-485 support
• IrDA mode (hardware encoder/decoder functions)
• Five External Interrupt Pins
• Parallel Master Port/Enhanced Parallel Slave Port (PMP/EPSP), 8-Bit Data with External Programmable Control (polarity and protocol)
• Enhanced CRC module
• Reference Clock Output with Programmable Divider
• Two Configurable Logic Cell (CLC) Blocks:
• Two inputs and one output, all mappable to peripherals or I/O pins
• AND/OR/XOR logic and D/JK flip-flop functions
• Peripheral Pin Select (PPS) with Independent I/O Mapping of Many Peripherals