PIC32CX1025SG41100T-I/E5X

This microcontroller integrates 1 MB Flash and 256 KB SRAM, with an optional Hardware Security Module supporting cryptographic functions, and features a 1 MSPS 12-bit ADC, QSPI, USB, Ethernet, and PTC. Operating conditions span 1.71V to 3.63V, with a maximum operating frequency of 120 MHz over the -40°C to +85°C temperature range and 100 MHz over the -40°C to +125°C range. The core features an Arm Cortex-M4F CPU running at up to 120 MHz, with 4 KB instruction and data caches, an 8-region MPU, FPU, and ETM. The memory system supports self-programmable Flash with ECC and dual-bank read-while-write, SRAM with ECC option, tightly coupled memory, and additional SRAM retainable in backup mode. Multiple low-power modes, sleep-wakeup peripherals, and an embedded buck/LDO regulator are provided. Up to 99 programmable I/O pins are available. Security features include a 256-bit AES engine supporting multiple modes, TRNG, Public Key Cryptography Controller, SHA-based Integrity Check Module, and an optional Hardware Security Module supporting secure boot, secure update, X.509 certificate handling, and various cryptographic algorithms such as ECDSA and RSA. The peripheral set is rich, including an event system, eight serial communication interfaces configurable as USART/I2C/SPI and more, multiple timer/counters, RTC, watchdog, CRC, I2S, position decoder, frequency meter, configurable custom logic, dual-channel 12-bit 1 Msps ADC and DAC, analog comparators, Parallel Capture Controller, and PTC supporting both self-capacitance and mutual-capacitance touch sensing. High-performance peripherals include a 32-channel DMA controller, two SD/MMC host controllers, one QSPI with XIP support, one Ethernet MAC with dedicated DMA and IEEE 1588 support, and two CAN controllers supporting CAN-FD.

Key features

• Operating conditions: 1.71V to 3.63V; up to 120 MHz at -40°C to +85°C; up to 100 MHz at -40°C to +125°C.
• Core: Arm Cortex-M4F CPU up to 120 MHz, delivering 403 CoreMark performance, with 4 KB instruction/data cache, 8-region MPU, FPU, and embedded trace module.
• Memory: 1 MB self-programmable Flash with ECC and dual-bank read-while-write support; 256 KB SRAM main memory (128 KB with optional ECC); up to 4 KB tightly coupled memory; 8 KB additional SRAM retainable in backup mode; eight 32-bit backup registers.
• Low power & power management: Multiple sleep modes including Idle, Standby, Hibernate, Backup, and Off; sleep-wakeup peripherals; battery backup support; embedded buck/LDO regulator with dynamic selection.
• I/O: Up to 99 programmable I/O pins.
• Security & cryptography: Integrated 256-bit AES engine supporting ECB, CBC, CFB, OFB, and CTR modes; true random number generator; public key cryptography controller and classic PKC library supporting RSA, DSA, and elliptic curve cryptography; integrity check module based on SHA1, SHA224, and SHA256; permanent protection for chip erase, boot region programming, and debug access, with optional immutable boot region.
• Optional hardware security module: Secure boot (host code image and signature verification) and secure update (secure key storage and image decryption); X.509 certificate storage, parsing, validation, and revocation; integrated high-speed SHA256, HMAC, and AES-CMAC engines; ECDSA sign/verify and ECDH key agreement for P224, P256, P384, SECP256K1, and 256-bit Brainpool curves; RSA 2048 sign/verify, 3072 verify, 1024 encrypt/decrypt; 256-bit symmetric key and 2048-bit RSA key generation and derivation; integrated NIST SP800-90 RNG.
• Peripherals: 32-channel event system; eight serial communication interfaces configurable as USART (ISO7816, LIN, RS485), I2C (up to 3.4 MHz), or SPI; eight 16-bit timer/counters (configurable as 16-bit, 8-bit, or 32-bit); two 24-bit and three 16-bit control timer/counters with extended features including PWM generation, fault protection, and dead-band control; 32-bit RTC; up to 5 wake-up pins with tamper detection and debounce filtering; watchdog timer with window mode; CRC-32 generator; one dual-channel I2S interface; quadrature decoder; frequency meter; four configurable custom logic blocks.
• Analog peripherals: Dual 12-bit 1 Msps ADC, up to 16 inputs per channel, differential and single-ended modes, automatic offset/gain compensation, hardware oversampling and decimation supporting 13 to 16-bit resolution; dual 12-bit 1 Msps DAC; two analog comparators with window mode; parallel capture controller (up to 14-bit wide).
• Touch control: Peripheral touch controller supporting capacitive touch buttons, sliders, and wheels, touch wake-up, up to 32 self-capacitance and 256 mutual-capacitance channels.
• High-performance peripherals: 32-channel DMA controller with built-in CRC generation/monitoring hardware; two SD/MMC host controllers supporting up to 50 MHz operation, compatible with SD/SDHC 3.01, SDIO 3.0, and MMC 4.51; one quad-SPI interface with XIP and dedicated AHB memory region; one Ethernet MAC supporting 10/100 Mbps, dedicated DMA, IEEE 1588 PTP, timestamp unit, IEEE 802.3az EEE, and wake-on-LAN; two CAN controllers supporting CAN 2.0A/B and CAN-FD.
• Connectivity: One full-speed (12 Mbps) USB interface.