PIC32MM0064GPL028-I/ML

Key features

• Low Pin Count Packages, ranging from 20 to 36 Pins, including UQFN as small as 4x4 mm
• Up to 64K Flash Memory:
• 20,000 erase/write cycle endurance
• 20 years minimum data retention
• Self-programmable under software control
• Up to 8K Data Memory
• Pin-Compatible with most PIC24 MCU/dsPIC DSC devices
• Multiple Interrupt Vectors with individually programmable priority
• Fail-Safe Clock Monitor mode
• Configurable Watchdog Timer with on-chip, low-power RC oscillator
• Programmable Code Protection
• Selectable Oscillator Options including:
• High-precision, 8 MHz internal Fast RC (FRC) oscillator
• High-speed crystal/resonator oscillator or external clock
• 2x/3x/4x/6x/12x/24x PLL, which can be clocked from the FRC or primary oscillator
• Atomic Set, Clear and Invert Operation on select Peripheral Registers
• High-Current Sink/Source 11 mA/16 mA on all ports
• Independent, low-power 32 kHz Timer Oscillator
• Two 4-Wire SPI modules (up to 25 MHz non-PPS, 20 MHz PPS):
• 16-byte FIFO
• I2S mode
• Two UARTs:
• RS-232, RS-485 and LIN/J2602 support
• IrDA with on-chip hardware encoder and decoder
• External Edge and Level Change Interrupt on all ports
• CRC module
• Hardware Real-Time Clock and Calendar (RTCC)
• Up to 20 Peripheral Pin Select (PPS) Remappable Pins
• Seven Total 16-Bit Timers:
• Timer1: Dedicated 16-bit timer/counter
• Two additional 16-bit timers in each MCCP and SCCP module
• Capture/Compare/PWM/Timer modules:
• Two 16-bit timers or one 32-bit timer in each module
• PWM resolution down to 21 ns
• One Multiple Output (MCCP) module:
• Flexible configuration as PWM, input capture, output compare or timers
• Six PWM outputs
• Programmable dead time
• Auto-shutdown
• Two Single Output (SCCP) modules:
• Flexible configuration as PWM, input capture, output compare or timers
• Single PWM output
• Reference Clock Output (REFO)
• Two Configurable Logic Cells (CLC) with Internal Connections to select Peripherals and PPS
• Two Programming and Debugging Interfaces:
• 2-wire ICSP interface with non-intrusive access and real-time data exchange with application
• 4-wire MIPS standard Enhanced JTAG interface
• IEEE Standard 1149.2 Compatible (JTAG) Boundary Scan
• Two Analog Comparators with Input Multiplexing
• Programmable High/Low-Voltage Detect (HLVD)
• 5-Bit DAC with Output Pin
• Up to 14-Channel, Software-Selectable 10/12-Bit SAR Analog-to-Digital Converter (ADC):
• 12-bit, up to 222k samples/second conversion rate
• 10-bit, up to 250k samples/second conversion rate
• Sleep mode operation
• Band gap reference input feature
• Windowed threshold compare feature
• Auto-scan feature
• Brown-out Reset (BOR)
• microAptiv UC 32-Bit Core with 5-Stage Pipeline
• microMIPS Instruction Set for 35% Smaller Code and 98% Performance compared to MIPS32 Instructions
• DC-25 MHz Operating Frequency
• 3.17 CoreMark/MHz (79 CoreMark) Performance
• 1.53 DMIPS/MHz (37 DMIPS) (Dhrystone 2.1) Performance
• 16-Bit/32-Bit Wide Instructions with 32-Bit Wide Data Path
• Two Sets of 32 Core Register Files (32-bit) to Reduce Interrupt Latency
• Single-Cycle 32x16 Multiply and Two-Cycle 32x32 Multiply
• Hardware Divide Unit
• 64-Bit, Zero Wait State Flash with ECC to Maximize Endurance/Retention
• Low-Power modes:
• Idle: CPU off, peripherals run from system clock
• Sleep: CPU and peripherals off
• Fast wake-up Sleep with retention
• Low-power Sleep with retention
• 0.5 μA Sleep Current for Regulator Retention mode and 5 μA for Regulator Standby mode
• On-Chip 1.8V Voltage Regulator (VREG)
• On-Chip Ultra Low-Power Retention Regulator