PIC32MX270F256B-I/ML

Key features

• MIPS16e mode for up to 40% smaller code size
• Code-efficient (C and Assembly) architecture
• Single-cycle (MAC) 32x16 and two-cycle 32x32 multiply
• 0.9% internal oscillator
• Programmable PLLs and oscillator clock sources
• Fail-Safe Clock Monitor (FSCM)
• Independent Watchdog Timer
• Fast wake-up and start-up
• Low-power management modes (Sleep and Idle)
• Integrated Power-on Reset and Brown-out Reset
• 0.5 mA/MHz dynamic current (typical)
• 44 μA IPD current (typical)
• Data communication: I²S, LJ, RJ, and DSP modes
• Control interface: SPI and I²C
• Master clock: Generation of fractional clock frequencies; Can be synchronized with USB clock; Can be tuned in run-time
• 10-bit 1.1 Msps rate with one S&H. Up to 10 analog inputs on 28-pin devices and 13 analog inputs on 44-pin devices
• Flexible and independent ADC trigger sources
• Charge Time Measurement Unit (CTMU): Supports mTouch capacitive touch sensing; Provides high-resolution time measurement (1 ns); On-chip temperature measurement capability
• Comparators: Up to three Analog Comparator modules; Programmable references with 32 voltage points
• Five General Purpose Timers: Five 16-bit and up to two 32-bit Timers/Counters
• Five Output Compare (OC) modules
• Five Input Capture (IC) modules
• Peripheral Pin Select (PPS) to allow function remap
• Real-Time Clock and Calendar (RTCC) module
• USB 2.0-compliant Full-speed OTG controller
• Two UART modules (12.5 Mbps): Supports LIN 2.0 protocols and IrDA support
• Two 4-wire SPI modules (25 Mbps)
• Two I²C modules (up to 1 Mbaud) with SMBus support
• PPS to allow function remap
• Parallel Master Port (PMP)
• Four channels of hardware DMA with automatic data size detection
• Two additional channels dedicated for USB
• Programmable Cyclic Redundancy Check (CRC)
• 10 mA source/sink on all I/O pins and up to 14 mA on non-standard VOH
• 5V-tolerant pins
• Selectable open drain, pull-ups, and pull-downs
• External interrupts on all I/O pins
• Class B Safety Library, IEC 60730
• In-circuit and in-application programming
• 4-wire MIPS Enhanced JTAG interface
• Unlimited program and six complex data breakpoints
• IEEE 1149.2-compatible (JTAG) boundary scan