R5F11CCCMBG#U0

Key features

• Ultra-low power consumption technology
• VDD = 2.4 to 5.5 V
• HALT mode
• STOP mode
• SNOOZE mode
• CISC architecture with 3-stage pipeline
• Minimum instruction execution time: Can be changed from high speed 0.03125 μs (@ 32 MHz operation with high-speed on-chip oscillator or PLL clock) to ultra-low speed (1 μs @ 1 MHz operation with high-speed on-chip oscillator or PLL clock)
• Multiply/divide/multiply & accumulate instructions are supported.
• Address space: 1 MB
• General-purpose registers: (8-bit register × 8) × 4 banks
• On-chip RAM: 8 KB
• Code flash memory: 32 KB
• Block size: 1 KB
• Prohibition of block erase and rewriting (security function)
• On-chip debug function
• Self-programming (with boot swap function/flash shield window function)
• Data flash memory: 4 KB
• Back ground operation (BGO): Instructions can be executed from the program memory while rewriting the data flash memory.
• Number of rewrites: 1,000,000 times (TYP.)
• Voltage of rewrites: VDD = 2.4 to 5.5 V
• High-speed on-chip oscillator: TA = -40 to +105 ℃ (G: Industrial applications), TA = -40 to +125 ℃ (M: Industrial applications)
• On-chip power-on-reset (POR) circuit
• On-chip voltage detector (LVD) (Select interrupt and reset from 7 levels)
• Transfer modes: Normal transfer mode, repeat transfer mode, block transfer mode
• Activation sources: Activated by interrupt sources.
• Chain transfer function
• Event signals of 16 types can be linked to the specified peripheral function.
• Simplified SPI(CSI): 2 channels
• UART: 2 channels (UART with LIN-bus supported: 1 channel)
• I2C/simplified I2C: 2 channels
• 16-bit timer: 8 channels (Timer Array Unit (TAU): 6 channels, timer RJ: 1 channel, timer RG: 1 channel)
• Interval timer: 1 channel
• Real-time clock: 1 channel (calendar for 99 years, alarm function, and clock correction function)
• Watchdog timer: 1 channel (operable with the dedicated low-speed on-chip oscillator)
• Sensor power supply (SBIAS) output: 0.5 V to 2.2 V
• 24-bit ΔΣ A/D converter with programmable gain instrumentation amplifier: 24-bit second-order ΔΣ A/D converter (AVDD = 2.7 to 5.5 V), SNDR: 85 dB (TYP.), Output data rate: 488 sps to 15.625 ksps in normal mode, 61 sps to 1.953 ksps in low power mode, Programmable gain instrumentation amplifier input: 3 or 4 channels (differential input mode or single-ended input mode can be specified for each input channel)
• DAC for offset adjustment
• Variable gain: x1 to x64
• On-chip temperature sensor
• 8-bit/10-bit successive approximation A/D converter (AVDD = 2.7 to 5.5 V)
• Analog input: 8 or 10 channels, sensor power supply (SBIAS), and internal reference voltage
• Internal reference voltage (1.45 V)
• Matrix configuration that consists of 3 operational amplifier channels and a configurable switch (AVDD = 2.7 to 5.5 V)
• Can be used as a 2- or 3-channel general operational amplifier
• Operational amplifier output: 3 channels
• General-purpose Analog I/O ports: 5 or 6 channels
• Offset voltage calibration
• 12-bit R-2R resistor ladder type D/A converter (AVDD = 2.7 to 5.5 V), Analog output: 1 channel (via configurable amplifier)
• CMOS I/O: 10 to 14 (N-ch open drain I/O [withstanding voltage of VDD]: 6, CMOS I/O: 7 to 11, CMOS input: 3)
• Can be set to TTL input buffer and on-chip pull-up resistor
• Different potential interface: Can connect to a 2.5/3 V device
• On-chip clock output/buzzer output controller
• On-chip BCD (binary-coded decimal) correction circuit