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R5F524TAADFM#11

RXv2 32 Bit 80MHz LFQFP-64(10x10) Microcontrollers RoHS

LFQFP-64(10x10)ROHS3 CompliantActive

80-MHz 32-bit RX MCUs, on-chip FPU, 153.6 DMIPS, 12-bit ADC, CAN

Manufacturer
RENESAS
Manufacturer part #
R5F524TAADFM#11
Store part #
C7334340
Package / case
LFQFP-64(10x10)
Packaging
Tray
Datasheet (PDF)

Every Order Guarantee

100% Authentic · 30-Day Return or Replacement · policy

10 in stock

#C7334340

Stock & price checked 2 days ago

QuantityUnit pricePack price
1+₹872.68₹872.68
10+₹852.74₹8,527.40
30+₹839.51₹25,185.30
100+₹826.28₹82,628.00

1 × ₹872.68

₹872.68

excl. GST

₹1,029.76 incl. 18% GST

Need volume or a scheduled delivery? Request a quote
  • Dispatch in 15-18 working days
  • GST invoice with every order
  • Standard pack: 1,280 per tray

R5F524TAADFM#11

₹872.68 for 1 + GST

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Specifications

DAC (Bit)
8bit
ADC (Bit)
12bit
Number of I/O
48
Operating Temperature
-40℃~+85℃
Program Memory Type
FLASH
Voltage - Supply
2.7V~5.5V
EEPROM
8KB
Program Storage Size
256KB
CPU Core
RXv2
Core Size
32 Bit
CPU Maximum Speed
80MHz
Oscillator Type
Built-in

Packaging & compliance

RoHS
ROHS3 Compliant
Lifecycle
Active
ECCN
3A991A2
Packaging
Tray
Standard pack
1,280 / Tray
Sold per
Piece
Minimum order
1
Unit weight
19.98 g

Overview

80-MHz 32-bit RX MCUs, on-chip FPU, 153.6 DMIPS, power supply 5 V, 12-bit ADC (equipped with 3-channel synchronous S/H circuits, double data registers, operating amplifiers, comparator) 3 units, Simultaneous sampling up to ADC 5 channels, CAN, 80-MHz PWM (three-phase complementary output × 2 channels + single-phase complementary output × 4 channels or three-phase complementary × 3 channels + single-phase complementary × 1 channel)

Key features

  • 32-bit RXv2 CPU core
  • Max. operating frequency: 80 MHz Capable of 153.6 DMIPS in operation at 80 MHz
  • Enhanced DSP: 32-bit multiply-accumulate and 16-bit multiply-subtract instructions supported
  • Built-in FPU: 32-bit single-precision floating point (compliant to IEEE754)
  • Divider (fastest instruction execution takes two CPU clock cycles)
  • Fast interrupt
  • CISC Harvard architecture with 5-stage pipeline
  • Variable-length instructions, ultra-compact code
  • On-chip debugging circuit
  • Memory protection unit (MPU) supported
  • Low power design and architecture
  • Operation from a single 2.7-V to 5.5-V supply
  • Three low power consumption modes
  • On-chip code flash memory
  • 512-/384-/256-/128-Kbyte capacities
  • On-board or off-board user programming
  • For instructions and operands
  • Clock functions
  • Main clock oscillator frequency: 1 to 20 MHz
  • External clock input frequency: Up to 20 MHz
  • PLL circuit input: 4 MHz to 12.5 MHz
  • On-chip low-speed oscillators, On-chip high-speed oscillators, dedicated on-chip oscillator for the IWDT
  • Clock frequency accuracy measurement circuit (CAC)
  • Independent watchdog timer
  • 15-kHz on-chip oscillator produces a dedicated clock signal to drive IWDT operation.
  • Up to 6 communications channels
  • CAN (compliant with ISO11898-1), incorporating 16 message boxes (1 channel)
  • SCI with many useful functions (3 channels) Asynchronous mode, clock synchronous mode, smart card interface mode, simplified SPI, simplified I²C, and extended serial mode.
  • I²C bus interface: Transfer at up to 400 kbps, capable of SMBus operation (1 channel)
  • RSPI capable of high speed connection Transfer at up to 20 Mbps (1 channel)
  • Up to 25 extended-function timers
  • 16-bit MTU3: 80 MHz operation, input capture, output compare, three-phase complementary PWM×2 channels output, CPU-efficient complementary PWM, phase counting mode (nine channels)
  • 16-bit GPT: 80 MHz operation, input capture, output compare, PWM wave-form single-phase complementary × 4 channels output or three-phase × 1 channel + singlephase complementary × 1 channel output, comparator interlocking operation (count operation, PWM negate control) (4 channels)
  • 8-bit TMRs (8 channels)
  • 16-bit compare-match timers (4 channels)
  • 12-bit A/D converter: 22 channels in 3 units
  • Incorporating sample-and-hold circuit 12 bits × 3 units (unit 0: 5 channels, unit 1: 5 channels, unit 2: 12 channels)
  • Sampling time can be set for each channel
  • Group scan priority control mode (3 levels)
  • Self-diagnostic function and analog input disconnection detection assistance function (compliant to IEC60730)
  • Input signal amplitude by the programmable gain amplifier (4 channels)
  • ADC: 3-channel simultaneous sample-and-hold circuit (3 shunt method), double data register (1 shunt method), amplifier (4 channels), comparator (4 channels)
  • 8-bit D/A converter: 2 channels

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