R5F56218BDFB#10

Key features

• 32-bit RX CPU core, 165 DMIPS at up to 100 MHz
• Single-precision 32-bit IEEE-754 floating-point operations
• Accumulator: 32 × 32-bit operation yielding 64-bit result, completed in a single instruction
• Multiply-divide unit with multiple instructions supporting 32 × 32-bit multiplication in a single CPU clock cycle
• Interrupt response in as few as 5 CPU clock cycles
• CISC-Harvard architecture with 5-stage pipeline
• Variable-length instructions for extremely compact code
• Memory protection unit support
• Background JTAG debugging and high-speed trace support
• Single supply 2.7V to 3.6V operation
• 480 µA/MHz run mode current with all peripherals active
• Deep software standby mode with RTC
• Four low-power modes
• Main flash, zero wait states, 100 MHz operation, 10 nsec read cycle
• Zero wait states at full-speed CPU reads
• Available in 256K, 384K, and 512K byte capacities
• For instructions or operands
• Programming via USB, SCI, JTAG, or user code
• Data flash up to 32K bytes, supporting 30K erase cycles
• Background erase/program operations without CPU stalling
• SRAM with zero wait states, available in 64K or 96K byte capacities
• For operands or instructions
• Data retention in deep software standby mode
• Four fully programmable internal DMA channels
• Two EXDMA channels for external-to-external transfers
• Data transfer controller
• Power-on reset monitor/generator
• Low-voltage detection with precise settings
• System clock with clock monitor, external crystal 8 MHz to 14 MHz connected to internal PLL
• PLL source available to system, USB, and Ethernet
• Internal 125 kHz LOCO for IWDT
• External 32 kHz crystal for RTC
• Real-time clock with full calendar function, BCD format
• Two independent watchdog timers, 125 kHz LOCO operation
• Package options: TFLGA85 7 × 7 mm, 0.65 mm pitch; TFLGA145 9 × 9 mm, 0.65 mm pitch; LFBGA176 13 × 13 mm, 0.8 mm pitch; LQFP100 14 × 14 mm, 0.5 mm pitch; LQFP144 20 × 20 mm, 0.5 mm pitch
• Up to 14 communication interfaces
• USB 2.0 full-speed interface with PHY, host/function/OTG support, 10 endpoint types: control, interrupt, bulk, isochronous
• Ethernet MAC 10/100 Mbps, half- or full-duplex, dedicated DMA with 2K byte transmit and receive FIFOs, external PHY connection via RMII or MII interface
• CAN interface compliant with ISO11898-1, supporting 32 mailboxes
• SCI channels: asynchronous, clocked synchronous, smart card, and 9-bit modes
• I2C interface up to 1 Mbps with SMBus support
• RSPI interface
• External address space, eight chip-select areas, 128M byte SDRAM area
• Selectable 8-bit, 16-bit, or 32-bit bus width per area
• TFT-LCD support up to WQVGA resolution
• Up to 20 multi-function timers
• 16-bit MTU2 with input capture, output compare, PWM output, and phase counting modes
• 8-bit TMR
• 16-bit CMT
• 1 MHz ADC unit, two combination options
• 12-bit × 8-channel unit with single sample-and-hold circuit
• Or two 10-bit × 4-channel units, each with one sample-and-hold circuit
• AD conversion value addition mode
• 10-bit DAC, 2-channel
• Up to 128 GPIOs, 5V tolerant, open-drain, internal pull-up
• Operating temperature range: –40°C to +85°C