R7FA4T1BB3CFM#BA0

The RA4T1 Group delivers up to 100 MHz of CPU performance using an Arm Cortex - M33 core with a code flash memory ranging from 128 KB to 256 KB, 4 KB of data flash memory, and 40 KB of SRAM. The RA4T1 Group offers a wide set of peripherals, including CANFD, I3C, and ADC. The MCU integrates multiple series of software - and pin - compatible Arm - based 32 - bit cores that share a common set of Renesas peripherals to facilitate design scalability and efficient platform - based product development. The MCU in this series incorporates a high - performance Arm Cortex® - M33 core running up to 100 MHz with the following features: Up to 256 KB code flash memory, 40 KB SRAM, Analog peripherals, Security and safety features.

Key features

• Arm® Cortex® - M33 Core
• Armv8 - M architecture with the main extension
• Maximum operating frequency: 100 MHz
• Arm Memory Protection Unit (Arm MPU) – Protected Memory System Architecture (PMSAv8) – Secure MPU (MPU_S): 8 regions – Non - secure MPU (MPU_NS): 8 regions
• SysTick timer – Embeds two Systick timers: Secure and Non - secure instance – Driven by LOCO or system clock
• CoreSight™ ETM - M33
• Memory
• Up to 256 KB code flash memory
• 4 KB data flash memory (100,000 program/erase (P/E) cycles)
• 40 KB SRAM
• Connectivity
• Serial Communications Interface (SCI) x 2 – Asynchronous interfaces – 8 - bit clock synchronous interface – Smart card interface – Simple I2C – Simple SPI – Manchester coding
• I3C bus interface (I3C)
• Serial Peripheral Interface (SPI) x 2
• CAN with Flexible Data - rate (CANFD)
• Analog
• 12 - bit A/D Converter (ADC12) – Sample - and - hold circuits x 3 – Programmable Gain Amplifier x 3
• High - Speed Analog Comparator (ACMPHS) x 3
• 12 - bit D/A Converter (DAC12) x 2
• Temperature Sensor (TSN)
• Timers
• General PWM Timer 16 - bit Enhanced (GPT16E) x 6
• Low Power Asynchronous General Purpose Timer (AGT) x 2
• Security
• Arm® TrustZone® – Up to three regions for the code flash – Up to two regions for the data flash – Up to three regions for the SRAM – Individual secure or non - secure security attribution for each peripheral
• 128 - bit unique ID
• True Random Number Generator (TRNG)
• Pin function – Secure pin multiplexing
• System and Power Management
• Low power modes
• Event Link Controller (ELC)
• Data Transfer Controller (DTC)
• DMA Controller (DMAC) x 8
• Power - on reset
• Low Voltage Detection (LVD) with voltage settings
• Watchdog Timer (WDT)
• Independent Watchdog Timer (IWDT)
• Multiple Clock Sources
• Main clock oscillator (MOSC) (8 to 24 MHz)
• Sub - clock oscillator (SOSC) (32.768 kHz)
• High - speed on - chip oscillator (HOCO) (16/18/20 MHz)
• Middle - speed on - chip oscillator (MOCO) (8 MHz)
• Low - speed on - chip oscillator (LOCO) (32.768 kHz)
• IWDT - dedicated on - chip oscillator (15 kHz)
• Clock trim function for HOCO/MOCO/LOCO
• PLL
• Clock out support
• General - Purpose I/O Ports
• 5 - V tolerance, open drain, input pull - up, switchable driving ability
• Operating Voltage
• VCC: 2.7 to 3.6 V
• Operating Temperature and Packages
• Ta = -40°C to +105°C
• 64 - pin LQFP (10 mm x 10 mm, 0.5 mm pitch)
• 48 - pin LQFP (7 mm x 7 mm, 0.5 mm pitch)
• 48 - pin QFN (7 mm x 7 mm, 0.5 mm pitch)
• 32 - pin LQFP (7 mm x 7 mm, 0.8 mm pitch)
• 32 - pin QFN (5 mm x 5 mm, 0.5 mm pitch)