R7FA6E10D2CFP#AA0

High-performance 200 MHz Arm Cortex-M33 core, up to 1 MB code flash memory with Dual-bank, background and SWAP operation, 8 KB Data flash memory, and 256 KB SRAM with Parity. High-integration with Ethernet MAC controller, USB 2.0 Full-Speed, SDHI, Quad SPI, and advanced analog.

Key features

• Armv8-M architecture with the main extension
• Maximum operating frequency: 200 MHz
• Arm Memory Protection Unit (Arm MPU) – Protected Memory System Architecture (PMSAv8) – Secure MPU (MPU_S): 8 regions – Non-secure MPU (MPU_NS): 8 regions
• SysTick timer – Embeds two Systick timers: Secure and Non-secure instance – Driven by LOCO or system clock
• CoreSight ETM-M33
• Memory: Up to 1-MB code flash memory
• 8-KB data flash memory (100,000 program/erase (P/E) cycles)
• 256-KB SRAM
• Connectivity: Serial Communications Interface (SCI)×6 – Asynchronous interfaces – 8-bit clock synchronous interface – Smart card interface – Simple IIC – Simple SPI – Manchester coding (SCI3, SCI4)
• I²C bus interface (IIC)×2
• Serial Peripheral Interface (SPI)×2
• Quad Serial Peripheral Interface (QSPI)
• USB 2.0 Full-Speed Module (USBFS)
• Control Area Network module (CAN)
• Ethernet MAC/DMA Controller (ETHERC/EDMAC)
• SD/MMC Host Interface (SDHI)
• Serial Sound Interface Enhanced (SSIE)
• Analog: 12-bit A/D Converter (ADC12)
• 12-bit D/A Converter (DAC12)
• Timers: General PWM Timer 32-bit (GPT32)×2
• General PWM Timer 16-bit (GPTl6)×4
• Low Power Asynchronous General Purpose Timer (AGT)×6
• Security and Encryption: Arm TrustZone – Up to three or six regions for the code flash, depending on the bank mode – Up to two regions for the data flash – Up to three regions for the SRAM – Individual secure or non-secure security attribution for each peripheral
• System and Power Management: Low power modes
• Battery backup function (VBATT)
• Realtime Clock (RTC) with calendar and VBATT support
• Event Link Controller (ELC)
• Data Transfer Controller (DTC)
• DMA Controller (DMAC)×8
• Power-on reset
• Low Voltage Detection (LVD) with voltage settings
• Watchdog Timer (WDT)
• Independent Watchdog Timer (IWDT)
• Multiple Clock Sources: Main clock oscillator (MOSC) (8 to 24 MHz)
• Sub-clock oscillator (SOSC) (32.768 kHz)
• High-speed on-chip oscillator (HOCO) (16/18/20 MHz)
• Middle-speed on-chip oscillator (MOCO) (8 MHz)
• Low-speed on-chip oscillator (LOCO) (32.768 kHz)
• IWDT-dedicated on-chip oscillator (15 kHz)
• Clock trim function for HOCO/MOCO/LOCO
• PLL/PLL2
• Clock out support
• General-Purpose I/O Ports: 5-V tolerance, open drain, input pull-up, switchable driving ability
• Operating Voltage: VCC: 2.7 to 3.6 V
• Operating Temperature and Packages: Ta = -40℃ to +85℃ – 100-pin LQFP (14 mm×14 mm, 0.5 mm pitch) – 64-pin LQFP (10 mm×10 mm, 0.5 mm pitch) – 48-pin QFN (7 mm×7 mm, 0.5 mm pitch)