R7FA6M2AD3CFP#AA0

The MCU integrates multiple series of software- and pin-compatible Arm-based 32-bit cores that share a common set of Renesas peripherals to facilitate design scalability and efficient platform-based product development. The MCU in this series incorporates a high-performance Arm Cortex-M4 core running up to 120 MHz with the following features: Up to 1-MB code flash memory 384-KB SRAM Capacitive Touch Sensing Unit (CTSU) Ethernet MAC Controller (ETHERC), USBFS, SD/MMC Host Interface Quad Serial Peripheral Interface (QSPI) Security and safety features 12-bit A/D Converter (ADC12) 12-bit D/A Converter (DAC12) Analog peripherals.

Key features

• Armv7E-M architecture with DSP instruction set
• Maximum operating frequency: 120 MHz
• Support for 4-GB address space
• On-chip debugging system: JTAG, SWD, and ETM
• Boundary scan and Arm Memory Protection Unit (Arm MPU)
• Up to 1-MB code flash memory (40 MHz zero wait states)
• 32-KB data flash memory (125,000 erase/write cycles)
• Up to 384-KB SRAM
• Flash Cache (FCACHE)
• Memory Protection Units (MPU)
• Memory Mirror Function (MMF)
• 128-bit unique ID
• Ethernet MAC Controller (ETHERC)
• Ethernet DMA Controller (EDMAC)
• USB 2.0 Full-Speed (USBFS) module - On-chip transceiver
• Serial Communications Interface (SCI) with FIFO×10
• Serial Peripheral Interface (SPI)×2
• I²C bus interface (IIC)×3
• Controller Area Network (CAN)×2
• Serial Sound Interface Enhanced (SSIE)
• SD/MMC Host Interface (SDHI)×2
• Quad Serial Peripheral Interface (QSPI)
• IrDA interface
• Sampling Rate Converter (SRC)
• External address space - 8-bit or 16-bit bus space is selectable per area - SDRAM support
• 12-bit A/D Converter (ADC12) with 3 sample-and-hold circuits each × 2
• 12-bit D/A Converter (DAC12)×2
• High-Speed Analog Comparator (ACMPHS)×6
• Temperature Sensor (TSN)
• General PWM Timer 32-bit Enhanced High Resolution (GPT32EH)×4
• General PWM Timer 32-bit Enhanced (GPT32E)×4
• General PWM Timer 32-bit (GPT32)×6
• Asynchronous General-Purpose Timer (AGT)×2
• Watchdog Timer (WDT)
• Error Correction Code (ECC) in SRAM
• SRAM parity error check
• Flash area protection
• ADC self-diagnosis function
• Clock Frequency Accuracy Measurement Circuit (CAC)
• Cyclic Redundancy Check (CRC) calculator
• Data Operation Circuit (DOC)
• Port Output Enable for GPT (POEG)
• Independent Watchdog Timer (IWDT)
• GPIO readback level detection
• Register write protection
• Main oscillator stop detection
• Illegal memory access
• Low power modes
• Realtime Clock (RTC) with calendar and VBATT support
• Event Link Controller (ELC)
• DMA Controller (DMAC)×8
• Data Transfer Controller (DTC)
• Key Interrupt Function (KINT)
• Power-on reset
• Low Voltage Detection (LVD) with voltage settings
• AES128/192/256
• 3DES/ARC4
• SHA1/SHA224/SHA256/MD5
• GHASH
• RSA/DSA/ECC
• True Random Number Generator (TRNG)
• Capacitive Touch Sensing Unit (CTSU)
• Parallel Data Capture Unit (PDC)
• Main clock oscillator (MOSC) (8 to 24 MHz)
• Sub-clock oscillator (SOSC) (32.768 kHz)
• High-speed on-chip oscillator (HOCO) (16/18/20 MHz)
• Middle-speed on-chip oscillator (MOCO) (8 MHz)
• Low-speed on-chip oscillator (LOCO) (32.768 kHz)
• IWDT-dedicated on-chip oscillator (15 kHz)
• Clock trim function for HOCO/MOCO/LOCO
• Clock out support
• Up to 110 input/output pins - Up to 1 CMOS input - Up to 109 CMOS input/output - Up to 21 input/output 5 V tolerant - Up to 18 high current (20 mA)
• Ta = -40℃ to +85℃ - 145-pin LGA (7 mm×7 mm, 0.5 mm pitch)
• Ta = -40℃ to +105℃ - 144-pin LQFP (20 mm×20 mm, 0.5 mm pitch) - 100-pin LQFP (14 mm×14 mm, 0.5 mm pitch)