RM48L540DPGETR

The RM48Lx40 device is a high-performance microcontroller family designed for safety systems. The safety architecture includes: dual-core CPU operating in lockstep mode; CPU and memory built-in self-test (BIST) logic; ECC on flash and data SRAM; parity on peripheral memory; and loopback capability on peripheral I/O. The RM48Lx40 device integrates an ARM Cortex-R4F floating-point CPU, which delivers an efficient 1.66 DMIPS/MHz and is configured to run at up to 200 MHz, providing up to 332 DMIPS. The device supports little-endian [LE] format. The RM48Lx40 device features up to 3MB of integrated flash memory and up to 256KB of data RAM, both supporting single-bit error correction and double-bit error detection. The on-chip flash memory is a non-volatile, electrically erasable and programmable memory implemented with a 64-bit wide data bus interface. For all read, program, and erase operations, the flash operates from a 3.3V supply input (same level as the I/O supply). In pipeline mode, the flash can operate at system clock frequencies up to 200 MHz. The SRAM supports single-cycle read and write access in byte, half-word, word, and double-word modes. The RM48Lx40 device features peripherals targeted at real-time control applications, including 2 Next Generation High End Timer (N2HET) timing coprocessors and 2 12-bit analog-to-digital converters (ADC) supporting up to 24 inputs each. N2HET1 is an advanced intelligent timer that provides precise timing capabilities for real-time applications. The timer is software-controlled, uses a reduced instruction set, and features a dedicated timer micromachine with an associated I/O port. N2HET can be used for PWM output, capture or compare input, and GPIO. N2HET is particularly suited for applications requiring multiple sensor inputs and driving actuators with complex, precise timing pulses. A High End Timer Transfer Unit (HTU) performs DMA-type operations to transfer N2HET data to and from main memory. An MPU is integrated within the HTU. The device features two 12-bit resolution MibADCs, each with 24 channels and a buffer RAM protected by 64-word parity. MibADC channels can be converted individually or grouped by software for sequential conversion sequences. 16 channels can be shared between the two MibADCs. There are three independent groups. Each sequence can be converted once when triggered or configured for continuous conversion mode. The device provides multiple communication interfaces: 3 MibSPI, 2 SPI, 1 LIN, 1 SCI, 3 DCAN, 1 I2C, and 1 Ethernet. SPI provides a convenient method for high-speed serial communication between shift-register-type devices. LIN supports the Local Interconnect Standard 2.0 and can be used as a full-duplex UART using standard non-return-to-zero (NRZ) format. DCAN supports the CAN 2.0 (A and B) protocol standard and uses a serial, multi-master communication protocol that efficiently supports distributed real-time control at robust communication rates of up to 1 Mbps. DCAN is well-suited for systems operating in noisy and harsh environments (e.g., automotive network interconnects and industrial applications) that require reliable serial communication or multiplexed wiring. RMII and MDIO interfaces. The I2C module is a multi-master communication module that provides an interface between the microcontroller and an I2C-compatible device via the I2C serial bus. This I2C supports speeds of 100 Kbps and 400 Kbps. The frequency-modulated phase-locked loop (FMPLL) clock module is used to multiply an external frequency reference to a higher frequency for internal use. There are two FMPLL modules on this device. When enabled, these modules provide two of seven possible clock sources to the Global Clock Module (GCM). The GCM manages the mapping between available clock sources and device clock domains. The device also includes an External Clock Prescaler (ECP) module that, when enabled, outputs a continuous external clock on the ECLK pin/ball. The ECLK frequency is a user-programmable ratio of the peripheral interface clock (VCLK) frequency. This externally monitorable low-frequency output serves as an indicator of the device's operating frequency. The DMA controller has 16 channels, 32 control packets, and parity protection for its memory. An MPU is integrated within the DMA to restrict DMA access to designated memory regions and protect the remainder of the memory system from DMA faults. The Error Signaling Module (ESM) monitors all device errors and, upon detecting a fault, determines whether to generate an interrupt or assert an external ERROR pin. The ERROR pin can be monitored externally as an indicator of fault conditions within the microcontroller. The External Memory Interface (EMIF) provides off-chip expansion capability, enabling interfacing with synchronous DRAM (SDRAM) devices, asynchronous memory, peripherals, or FPGA devices. Several interfaces are implemented to enhance the debug capability of application code. In addition to the built-in ARM Cortex-R4F CoreSight debug features, an External Trace Macrocell (ETM) provides instruction and data tracing of program execution. For instrumentation purposes, a RAM Trace Port module (RTP) is implemented to support high-speed tracing of RAM and peripherals accessed by the CPU or any other master. A Data Modification Module (DMM) provides the capability to write external data to device memory. The RTP and DMM have no or minimal impact on the program execution time of application code. A Parameter Overlay Module (POM) can reroute flash accesses to internal memory or EMIF. This rerouting enables dynamic calibration of parameters and tables against production code without requiring code rebuilds to explicitly access RAM or halting the processor to re-program data flash. With its integrated safety features and broad selection of communication and control peripherals, the RM48Lx40 device is an ideal solution for high-performance real-time control applications with safety-critical requirements.

Applications

• Industrial safety applications
• Industrial automation safety PLC
• Power generation and distribution
• Turbines and wind engines
• Elevators and escalators
• Medical applications
• Ventilators
• Defibrillators
• Infusion pumps and insulin pumps
• Radiation therapy robots
• Surgical procedures

Key features

• High-performance microcontroller for safety-critical applications
• Dual CPU cores running in lockstep
• ECC on flash and RAM interfaces
• Built-in CPU and on-chip RAM self-test
• Error Signaling Module (ESM) with error pin
• Voltage and clock monitoring
• ARM Cortex–R4F 32-bit RISC CPU
• High-efficiency 1.66DMIPS/MHz with 8-stage pipeline
• FPU supporting single- and double-precision floating-point operations
• 12-region Memory Protection Unit (MPU)
• Open architecture with third-party support
• Up to 200MHz system clock
• Core supply voltage (VCC): 1.2V nominal
• I/O supply voltage (VCCOI): 3.3V nominal
• ADC supply voltage (VCCAD): 3.0 to 5.25V
• Up to 3MB program flash with ECC
• Up to 256KB RAM with ECC
• 64KB flash with ECC for emulated EEPROM
• 16-bit external memory interface
• Common platform architecture
• Consistent memory map across device family
• Real-Time Interrupt (RTI) OS timer
• 96-channel Vector Interrupt Module (VIM)
• 2-channel CRC checker
• DMA controller
• 16-channel and 32 control data packets
• Parity protection on control packet RAM
• DMA access protected by dedicated MPU
• FMPLL with built-in cycle-slip detector
• Independent non-modulated PLL
• IEEE 1149.1 JTAG, boundary scan, and ARM CoreSight components
• JTAG Security Module
• Trace and calibration features
• Embedded Trace Macrocell (ETM–R4)
• Data Modification Module (DMM)
• RAM Trace Port (RTP)
• Parameter Override Module (POM)
• 10/100Mbps Ethernet MAC (EMAC)
• IEEE 802.3 compliant (3.3V I/O only)
• MII, RMII, and MDIO support
• 3× CAN controllers (DCAN)
• 64 mailboxes, each with parity protection
• CAN protocol 2.0B compatible
• LIN interface controller
• LIN protocol version 2.1 compatible
• Configurable as second SCI
• Standard SCI
• I2C
• 3× MibSPI
• 128 words, each with parity protection
• 2× standard SPI
• 2× High-End Timer modules (N2HET)
• N2HET1: 32 programmable channels
• N2HET2: 18 programmable channels
• 160-word instruction RAM, each with parity protection
• Hardware angle generator per N2HET
• Dedicated Transfer Unit with MPU per N2HET (HTU)
• 2× 10- or 12-bit MibADC modules
• ADC1: 24 channels
• ADC2: 16 channels shared with ADC1
• 64 result buffers, each with parity protection
• 16 GPIO pins capable of generating interrupts
• Package options
• 144-pin QFP (PGE) [Green]
• 337-ball BGA (ZWT) [Green]