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SPC560D30L1B4E0X ST
ST

SPC560D30L1B4E0X

Freescale Series 32 Bit 48MHz LQFP-64(10x10) Microcontrollers RoHS

LQFP-64(10x10)ROHS3 CompliantActive

Chip Functional Characteristics for Automotive Body Electronics Applications

Manufacturer
ST
Manufacturer part #
SPC560D30L1B4E0X
Store part #
C2969942
Package / case
LQFP-64(10x10)
Packaging
Tape & Reel (TR)
Datasheet (PDF)

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100% Authentic · 30-Day Return or Replacement · policy

10 in stock

#C2969942

Stock & price checked 3 days ago

QuantityUnit pricePack price
1+₹1,029.07₹1,029.07
10+₹1,004.30₹10,043.00
30+₹988.00₹29,640.00
100+₹971.49₹97,149.00

1 × ₹1,029.07

₹1,029.07

excl. GST

₹1,214.30 incl. 18% GST

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  • Standard pack: 1,000 per reel

SPC560D30L1B4E0X

₹1,029.07 for 1 + GST

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Specifications

ADC (Bit)
12bit
Number of I/O
45
Operating Temperature
-40℃~+105℃
Program Memory Type
FLASH
Voltage - Supply
3V~5.5V
Program Storage Size
128KB
CPU Core
Freescale Series
Core Size
32 Bit
CPU Maximum Speed
48MHz
Oscillator Type
Built-in

Packaging & compliance

RoHS
ROHS3 Compliant
Lifecycle
Active
ECCN
3A991A2
Packaging
Tape & Reel (TR)
Standard pack
1,000 / Reel
Sold per
Piece
Minimum order
1
Unit weight
0.512 g

Overview

These 32-bit automotive microcontrollers are a family of system-on-chip (SoC) devices designed to be central to the development of the next wave of central vehicle body controller, smart junction box, front module, peripheral body, door control and seat control applications. This family is one of a series of next-generation integrated automotive microcontrollers based on the Power Architecture technology and designed specifically for embedded applications. The advanced and cost-efficient e200z0h host processor core of this automotive controller family complies with the Power Architecture technology and only implements the VLE (variable-length encoding) APU (auxiliary processing unit) and provides improved code density. It operates at speed of up to 48 MHz and offers high performance processing optimized for low power consumption. It capitalizes on the available development infrastructure of current power architecture devices and is supported with software drivers, operating systems and configuration code to assist with the user’s implementations. The device platform has a single level of memory hierarchy and can support a wide range of on-chip static random access memory (SRAM) and internal flash memory.

Applications

  • Central vehicle body controller
  • Smart junction box
  • Front module
  • Peripheral body
  • Door control
  • Seat control

Key features

  • AEC-Q100 qualified
  • High-performance up to 48 MHz e200z0h CPU – 32-bit Power Architecture technology CPU – Variable length encoding (VLE)
  • Memory – Up to 256 KB Code Flash with ECC – Up to 64 (4x16) KB Data Flash with ECC – Up to 16 KB SRAM with ECC
  • Interrupts – 16 priority levels Non-maskable interrupt (NMI) – Up to 38 external interrupts including 18 wakeup lines
  • 16-channel eDMA
  • GPIOs: 45 (LQFP64), 79 (LQFP100)
  • Timer units – 4-channel 32-bit periodic interrupt timers 4-channel 32-bit system timer module – System watchdog timer – 32-bit real-time clock timer 16-bit counter time-triggered I/Os – Up to 28 channels with PWM/MC/IC/OC – 5 independent counters – 27-channels with ADC trigger capability
  • 12-bit analog-to-digital converter (ADC) with up to 33 channels – Up to 61 channels via external multiplexing – Individual conversion registers
  • Cross triggering unit (CTU)
  • Dedicated diagnostic module for lighting
  • Advanced PWM generation Time-triggered diagnostics PWM-synchronized ADC measurements
  • Communications interfaces
  • 1 FlexCAN interface (2.0B active) with 32 message buffers
  • 3 LINFlex/UART, 1 with DMA capability
  • 2 DSPI
  • Clock generation
  • 4 to 16 MHz fast external crystal oscillator
  • 16 MHz fast internal RC oscillator
  • 128 kHz slow internal RC oscillator
  • Software-controlled FMPLL
  • Clock monitoring unit
  • On-chip CAN/UART bootstrap loader

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