SPC563M64L7COAR

These 32-bit automotive microcontrollers are a family of system-on-chip (SoC) devices that contain all the features of the SPC563Mxx family and many new features coupled with high performance 90 nm CMOS technology to provide substantial reduction of cost per feature and significant performance improvement. The advanced and cost-efficient host processor core of this automotive controller family is built on Power Architecture technology. This family contains enhancements that improve the architecture’s fit in embedded applications, includes additional instruction support for digital signal processing (DSP), integrates technologies — such as an enhanced time processor unit, enhanced queued analog-to-digital converter, Controller Area Network, and an enhanced modular input-output system — that are important for today’s lower-end powertrain applications. The device has a single level of memory hierarchy consisting of up to 94 KB on-chip SRAM and up to 1.5 MB of internal flash memory. The device also has an external bus interface (EBI) for ‘calibration’. This external bus interface has been designed to support most of the standard memories used with the SPC564Axx and SPC563Mxx families. The host processor core of the SPC563Mxx complies with the Power Architecture Book E. It is 100% user mode compatible (with floating point library) with the classic Power Architecture instruction set. The Book E architecture has enhancements that improve the Power Architecture’s fit in embedded applications. In addition to the classic Power Architecture instruction set, this core also has additional instruction support for digital signal processing (DSP). The SPC563Mxx has a single level of memory hierarchy consisting of up to 94 KB on-chip SRAM and up to 1.5 MB of internal Flash memory.

Key features

• Single issue, 32-bit Power Architecture® Book E compliant e200z335 CPU core complex Includes variable length encoding (VLE) enhancements for code size reduction
• 32-channel direct memory access controller (DMA)
• Interrupt controller (INTC) capable of handling 364 selectable-priority interrupt sources: 191 peripheral interrupt sources, 8 software interrupts and 165 reserved interrupts.
• Frequency-modulated phase-locked loop (FMPLL)
• Calibration external bus interface (EBI)
• System integration unit (SIU)
• Up to 1.5 Mbyte on-chip Flash with Flash controller Fetch Accelerator for single cycle Flash access @80 MHz
• Up to 94 Kbyte on-chip static RAM (including up to 32 Kbyte standby RAM)
• Boot assist module (BAM)
• 32-channel second-generation enhanced time processor unit (eTPU) – 32 standard eTPU channels
• Architectural enhancements to improve code efficiency and added flexibility
• 16-channels enhanced modular input-output system (eMIOS)
• Enhanced queued analog-to-digital converter (eQADC)
• Decimation filter (part of eQADC)
• Silicon die temperature sensor
• 2 deserial serial peripheral interface (DSPI) modules (compatible with Microsecond Bus)
• 2 enhanced serial communication interface (eSCI) modules compatible with LIN
• 2 controller area network (FlexCAN) modules that support CAN 2.0B
• Nexus port controller (NPC) per IEEE-ISTO 5001-2003 standard
• IEEE 1149.1 (JTAG) support
• Nexus interface
• On-chip voltage regulator controller that provides 1.2 V and 3.3 V internal supplies from a 5 V external source.
• Designed for LQFP100, LQFP144, LQFP176 and LBGA208 packages.