SPC564A80L7CFAR

32-bit MCU series built on embedded Power Architecture®, available in LQFP176, LBGA208, PBGA324 packages and Known Good Die (KGD).

Key features

• 0 MHz e200z4 Power Architecture core Varia
• Superscalar architecture with 2 execution units
• Up to 2 integer or floating point instructions per cycle
• Up to 4 multiply per cycle
• 4 MB on - chip flash memory with E Read While Write (RWW)
• 192 KB on - chip RAM with standby functionality (32 KB)
• 14 + 3 KB instruction cache (with line locking) configurable as 2 - or 4 - way
• 14 + 3 KB eTP
• 5 x 4 crossbar switch (XBAR)
• 24 - entry MM
• External Bus Int masterport l Safe Protection 16 - entry Memory Protection
• CRC
• Junction temperature sensor errupts
• Configurable: 3 x eSCI, 3 x DSP, 3 x eSCI
• 3 SPI (2 of which sup)
• 1 x 200PBGAS24QFP176
• 3 x FlexCAN with 64 messages each
• 1 x FlexRay module (V2.1)
• 1 x eMIOS
• 1 x eTPU2
• 1 x eTPU2 (second)
• 2 enhanced queued analog - to - digital converters (eQADCs)
• On - chip CAN³⁺ I/FlexRay Bootstrap loader
• Nexus: Class S+ for core, Class T for the STAd (S - pm)
• Development Trigger Snapshot (Dl ck generation)
• On - chip 4–40 MHz
• On - chip FMPLL (frequency - mod. phase - locked loop) up to 120
• Power reduction mode: by modes
• Flexible supply scheme 5 V si
• Multiple external supply: 5 V, 3.3 V and 1.2 V