SPC570S50E1CEFAR

Freescale Series 32 Bit 80MHz TQFP-64(10x10) Microcontrollers RoHS

TQFP-64(10x10)ROHS3 CompliantActive

32-bit PowerArchitecture technology CPU supporting multiple communication interfaces and security mechanisms

Manufacturer: ST
Manufacturer part #: SPC570S50E1CEFAR
Store part #: C2859324
Package / case: TQFP-64(10x10)
Category: Microcontrollers
Packaging: Tape & Reel (TR)

Datasheet (PDF)

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19 in stock

#C2859324

Stock & price checked 5 days ago

Quantity	Unit price	Pack price
1+	₹1,934.17	₹1,934.17
10+	₹1,845.48	₹18,454.80
30+	₹1,691.80	₹50,754.00
100+	₹1,557.57	₹1,55,757.00

Quantity (min 1)

1 × ₹1,934.17

₹1,934.17

excl. GST

₹2,282.32 incl. 18% GST

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Standard pack: 1,000 per reel

SPC570S50E1CEFAR

₹1,934.17 for 1 + GST

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Specifications

ADC (Bit): 12bit
Operating Temperature: -40℃~+125℃@(TJ)
Program Memory Type: FLASH
Voltage - Supply: 2.7V~5.5V
EEPROM: 32KB
Program Storage Size: 512KB
CPU Core: Freescale Series
Core Size: 32 Bit
CPU Maximum Speed: 80MHz
Oscillator Type: External

Packaging & compliance

RoHS: ROHS3 Compliant
Lifecycle: Active
ECCN: 3A991A2
Packaging: Tape & Reel (TR)
Standard pack: 1,000 / Reel
Sold per: Piece
Minimum order: 1
Unit weight: 0.4 g

Overview

Key features

AEC-Q100 qualified
High performance e200z0h dual core – 32-bit Power Architecture technology CPU
Core frequency as high as 80 MHz
Single issue 4-stage pipeline in-order execution core
Variable Length Encoding (VLE)
Up to 544 KB (512 KB code + 32 KB data, suitable for EEPROM emulation) on-chip flash memory: supports read during program and erase operations, and multiple blocks allowing EEPROM emulation
Up to 48 KB on-chip general-purpose SRAM
Multi-channel direct memory access controller (eDMA paired in lockstep) with 16 channels
Comprehensive new generation ASILD safety concept
Safety of bus masters (core + INTC, DMA) by delayed lockstep approach
Safety of storage (Flash, SRAM) by mainly ECC
Safety of the data path to storage and periphery by mainly End-to-End EDC (E2E EDC)
Clock and power, generation and distribution, supervised by dedicated monitors
Fault Collection and Control Unit (FCCU) for collection and reaction to failure notifications
Memory Error Management Unit (MEMU) for collection and reporting of error events in memories
Boot time MBIST and LBIST for latent faults
Check of safety mechanisms availability and error reaction path functionality by dedicated mechanisms
Safety of the periphery by application-level measures supported by replicated peripheral bridges and by LBIST
Further measures on dedicated peripherals (e.g. ADC supervisor)
Junction temperature sensor
8-region system memory protection unit (SMPU) with process ID support (tasks isolation)
Enhanced SW watchdog
Cyclic redundancy check (CRC) unit
Dual phase-locked loops with stable clock domain for peripherals and FM modulation domain for computational shell
Nexus Class 3 debug and trace interface
Communication interfaces: 2 LINFlexD modules, 3 deserial serial peripheral interface (DSPI) modules, and Up to 2 FlexCAN interfaces with 32 message buffers each
On-chip CAN/UART Bootstrap loader with Boot Assisted Flash (BAF). Physical Interface (PHY) can be UART and CAN
2 enhanced 12-bit SAR analog converters
1.5 μs conversion time (12 MHz)
16 physical channels (fully shared between the 2 SARADC units)
Supervisor ADC concept
Programmable Cross Triggering Unit (CTU)
Single 3.3 V or 5 V voltage supply
4 general purpose eTimer units (6 channels each)
Junction temperature range -40 °C to 150 °C (165 °C grade optional)