STM32F100RET6B

High-density value line, advanced Arm?-based 32-bit MCU with 256 to 512 KB Flash, 16 timers, ADC, DAC & 11 comm interfaces

Key features

• Core: Arm 32-bit Cortex-M3 CPU 24 MHz maximum frequency, 1.25 DMIPS /MHz (Dhrystone 2.1) performance Single-cycle multiplication and hardware division
• Memories: 256 to 512 Kbytes of Flash memory, 24 to 32 Kbytes of SRAM, Flexible static memory controller with 4 Chip Selects. Supports SRAM, PSRAM and NOR memories, LCD parallel interface, 8080/6800 modes
• Clock, reset and supply management: 2.0 to 3.6 V application supply and I/Os, POR, PDR and programmable voltage detector (PVD), 4-to-24 MHz crystal oscillator, Internal 8 MHz factory-trimmed RC, Internal 40 kHz RC, PLL for CPU clock, 32 kHz oscillator for RTC with calibration
• Low power: Sleep, Stop and Standby modes, VBAT supply for RTC and backup registers
• Serial wire debug (SWD) and JTAG I/F
• DMA: 12-channel DMA controller, Peripherals supported: timers, ADC, SPIs, I2Cs, USARTs and DACs
• 1x12-bit, 1.2 μs A/D converter (up to 16 ch.), Conversion range: 0 to 3.6 V, Temperature sensor
• 2x12-bit D/A converters
• Up to 112 fast I/O ports: 51/80/112 I/Os, all mappable on 16 external interrupt vectors and almost all 5 V-tolerant
• Up to 16 timers
• Up to seven 16-bit timers, each with up to 4 IC/OC/PWM or pulse counter
• One 16-bit, 6-channel advanced-control timer: up to 6 channels for PWM output, dead time generation and emergency stop
• One 16-bit timer, with 2 IC/OC, 1 OCN/PwM, dead-time generation and emergency stop
• Two 16-bit timers, each with IC/OC/OCN/PWM, dead-time generation and emergency stop
• Two watchdog timers
• SysTick timer: 24-bit downcounter
• Two 16-bit basic timers to drive the DAC
• Up to 11 communications interfaces
• Up to two I2C interfaces (SMBus/PMBus)
• Up to 3 USARTs (ISO 7816 interface, LIN, IrDA capability, modem control)
• Up to 2 UARTs
• Up to 3 SPIs (12 Mbit/s)
• Consumer electronics control (CEC) I/F
• CRC calculation unit, 96-bit unique ID