STM32F205RET7

Arm-based 32-bit MCU, 150 DMIPs, up to 1MB Flash/128+4KB RAM, with USB OTG HS/FS, Ethernet, 17 timers, 3 ADCs, 15 communication interfaces, and camera interface.

Key features

• Core: Arm 32-bit Cortex-M3 CPU (120 MHz max) with Adaptive real-time accelerator (ART Accelerator) allowing 0-wait state execution performance from Flash memory, MPU, 150 DMIPS/1.25 DMIPS/MHz (Dhrystone 2.1)
• Memories – Up to 1 Mbyte of Flash memory – 512 bytes of OTP memory – Up to 128+4 Kbytes of SRAM – Flexible static memory controller that supports Compact Flash, SRAM, PSRAM, NOR and NAND memories – LCD parallel interface, 8080/6800 modes
• Clock, reset and supply management – From 1.8 to 3.6 V application supply + I/Os – POR, PDR, PVD and BOR – 4 to 26 MHz crystal oscillator – Internal 16 MHz factory-trimmed RC – 32 kHz oscillator for RTC with calibration – Internal 32 kHz RC with calibration
• Low-power modes – Sleep, Stop and Standby modes – VBAT supply for RTC, 20x32 bit backup registers, and optional 4 Kbytes backup SRAM
• 3x12-bit, 0.5 µs ADCs with up to 24 channels and up to 6 MSPS in triple interleaved mode
• 2x12-bit D/A converters
• General-purpose DMA: 16-stream controller with centralized FIFOs and burst support
• Up to 17 timers – Up to twelve 16-bit and two 32-bit timers, up to 120 MHz, each with up to four IC/OC/PWM or pulse counter and quadrature (incremental) encoder input
• Debug mode: Serial wire debug (SWD), JTAG, and Cortex-M3 Embedded Trace Macrocell
• Up to 140 I/O ports with interrupt capability: Up to 136 fast I/Os up to 60 MHz Up to 138 5 V-tolerant I/Os
• Up to 15 communication interfaces Up to three I²C interfaces (SMBus/PMBus) Up to four USARTs and two UARTs (7.5 Mbit/s, ISO 7816 interface, LIN, IrDA, modem control) Up to three SPIs (30 Mbit/s), two with muxed I²S to achieve audio class accuracy via audio PLL or external PLL 2xCAN interfaces (2.0B Active) SDIO interface
• Advanced connectivity USB 2.0 full-speed device/host/OTG controller with on-chip PHY USB 2.0 high-speed/full-speed device/host/OTG controller with dedicated DMA, on-chip full-speed PHY and ULPI 10/100 Ethernet MAC with dedicated DMA: supports IEEE 1588v2 hardware, MII/RMII
• 8- to 14-bit parallel camera interface (48 Mbyte/s max.)
• CRC calculation unit
• 96-bit unique ID