STM32G050C8T6

This is a 32-bit MCU based on the Arm® Cortex®-M0+ core, featuring up to 64 KB Flash, 18 KB SRAM, integrated communication interfaces, timers, ADC, and low-power management capabilities, with support for wide voltage range and multiple package options.

Key features

• Core: Arm 32-bit Cortex-M0+ CPU, frequency up to 64 MHz
• -40°C to 85°C operating temperature
• Up to 64 Kbytes of Flash memory with protection and securable area
• 18 Kbytes of SRAM (16 Kbytes with HW parity check)
• CRC calculation unit
• Voltage range: 2.0 V to 3.6 V
• Power-on/Power-down reset (POR/PDR)
• Low-power modes: Sleep, Stop, Standby
• VBAT supply for RTC and backup registers
• 4 to 48 MHz crystal oscillator
• 32 kHz crystal oscillator with calibration
• Internal 16 MHz RC with PLL option
• Internal 32 kHz RC oscillator (±5%)
• Up to 44 fast I/Os
• All mappable on external interrupt vectors
• Multiple 5 V-tolerant I/Os
• 7-channel DMA controller with flexible mapping
• 12-bit, 0.4 μs ADC (up to 16 ext. channels)
• Up to 16-bit with hardware oversampling
• Conversion range: 0 to 3.6V
• 14 timers (two 128 MHz capable): 16-bit for advanced motor control, one 32-bit and five 16-bit general-purpose, two basic 16-bit, two low-power 16-bit, two watchdogs, SysTick timer
• Calendar RTC with alarm and periodic wakeup from Stop/Standby
• Two I²C-bus interfaces supporting Fast-mode Plus (1 Mbit/s) with extra current sink, one supporting SMBus/PMBus and wakeup from Stop mode
• Two USARTs with master/slave synchronous SPI; one supporting ISO7816 interface, LIN, IPCA capability, auto baud rate detection and wakeup feature
• Two SPIs (32 Mbit/s) with 4- to 16-bit programmable bitframe, one multiplexed with I²S interface
• Development support: serial wire debug (SWD)
• 96-bit unique ID
• All packages ECOPACK 2 compliant