STM32H743IIT6

32-bit Arm® Cortex®-M7 480MHz microcontroller with up to 2MB Flash, up to 1MB RAM, and 46 communication and analog interfaces.

Key features

• Core: 32-bit Arm® Cortex®-M7 core with double-precision FPU and L1 cache (16KB data cache + 16KB instruction cache), up to 480MHz, MPU support, 1027 DMIPS/2.14 DMIPS/MHz (Dhrystone 2.1), and DSP instructions.
• Memory: Up to 2MB Flash (read-while-write support); up to 1MB RAM (including 192KB TCM RAM, up to 864KB user SRAM, 4KB backup domain SRAM); dual-mode Quad-SPI memory interface (up to 133MHz); flexible external memory controller (up to 32-bit data bus, supporting SRAM, PSRAM, SDRAM/LPSDR SDRAM, NOR/NAND Flash, up to 100MHz in synchronous mode); CRC calculation unit.
• Security: ROP, PC-ROP, active tamper protection.
• GPIO: Up to 168 I/O ports with interrupt capability.
• Reset and Power Management: Three independent power domains (individually clock-gated or powered down); application supply and I/O voltage range 1.62 to 3.6V; POR, PDR, PVD, and BOR; dedicated USB supply (internal 3.3V regulator powering internal PHY); embedded LDO regulator with configurable output scaling; voltage scaling in Run and Stop modes (6 configurable ranges); backup regulator (~0.9V); analog peripheral reference voltage/VREF+; low-power modes (Sleep, Stop, Standby, and VBAT modes with battery charging support).
• Low-Power Consumption: VBAT battery operating mode (with charging capability); CPU and domain power state monitoring pins; 2.95μA in Standby mode (backup SRAM off, RTC/LSE on).
• Clock Management: Internal oscillators (64MHz HSI, 48MHz HSI48, 4MHz CSI, 32kHz LSI); external oscillators (4–48MHz HSE, 32.768kHz LSE); 3 PLLs (1 system clock, 2 kernel clocks, fractional mode support).
• Interconnect Matrix: 3 bus matrices (1 AXI and 2 AHB); bridges (5× AHB2-APB, 2× AXI2-AHB).
• DMA Controllers: 4 DMA controllers (1 high-speed master MDMA with linked-list support; 2 dual-port DMAs with FIFO; 1 basic DMA with request routing capability).
• Communication Peripherals: Up to 35 communication peripherals (4× I2C FM+ interfaces; 4× USART/4× UART; 1× LPUART; 6× SPI; 4× SAI; SPDIFRX interface; SWPMI single-wire protocol master interface; MDIO slave interface; 2× SD/SDIO/MMC interfaces; 2× CAN controllers; 2× USB OTG interfaces; Ethernet MAC interface; HDMI-CEC; 8–14-bit camera interface).
• Analog Peripherals: 11 analog peripherals (3× ADC up to 16-bit resolution; 1× temperature sensor; 2× 12-bit DAC; 2× ultra-low-power comparators; 2× op-amps; 1× DFSDM).
• Graphics: LCD-TFT controller (up to XGA resolution); Chrom-ART hardware graphics accelerator (DMA2D); hardware JPEG codec.
• Timers and Watchdogs: Up to 22 timers and watchdogs (1× high-resolution timer; 2× 32-bit timers; 2× 16-bit advanced motor control timers; 10× 16-bit general-purpose timers; 5× 16-bit low-power timers; 2× watchdogs; 1× SysTick timer; RTC).
• Debug: SWD and JTAG interfaces; 4KB embedded trace buffer.
• Other: True RNG (3 oscillators each); 96-bit unique ID; all packages ECOPACK2 compliant.