STM32H7A3AII6Q

The STM32H7A3xI/G devices are based on the high-performance Arm® Cortex®-M7 32-bit RISC core, operating at up to 280 MHz.

Key features

• Core: 32-bit Arm® Cortex®-M7 core with double-precision FPU and L1 cache (16KB data cache + 16KB instruction cache), up to 280 MHz, MPU, 599 DMIPS/2.14 DMIPS/MHz (Dhrystone 2.1), DSP instructions supported
• Memory: Up to 2MB Flash (read-while-write supported) + 1KB OTP; ~1.4MB RAM (192KB TCM RAM including 64KB ITCM and 128KB DTCM, 1.18MB user SRAM, 4KB backup domain SRAM); 2× Octo-SPI interfaces (PSRAM/NOR, etc., SRD mode 140MHz, DTR mode 110MHz); flexible external memory controller (32-bit data bus, SRAM/PSRAM/NOR synchronous mode 125MHz, SDRAM/LPSDR, 8/16-bit NAND); CRC calculation unit
• Security: ROP, PC-ROP, active tamper, secure firmware upgrade support
• General-purpose I/O: Up to 168 I/O ports with interrupt capability; fast I/O up to 133MHz; up to 164 5V-tolerant I/Os
• Low power: Stop mode down to 32μA (full RAM retention); Standby mode 2.8μA (backup SRAM off, RTC/LSE on, PDR off); VBAT mode 0.8μA (RTC and LSE on)
• Clock management: Internal oscillators (64MHz HSI, 48MHz HSI48, 4MHz CSI, 32kHz LSI); external oscillators (4–50MHz HSE, 32.768kHz LSE); 3× PLLs (1 for system clock, 2 for kernel clock, fractional mode supported)
• Power management: 2 independent power domains (CPU domain and smart run domain, independent clock gating); 1.62 to 3.6V application supply and I/Os; POR, PDR, PVD, BOR; dedicated USB supply (built-in 3.3V regulator); dedicated SDMMC supply; high-efficiency SMPS step-down converter (for VCORE or external circuits); embedded LDO (configurable output); voltage scaling in Run and Stop modes; backup regulator (~0.9V); low-power modes (Sleep, Stop, Standby); VBAT battery mode (with charging capability); CPU and domain power status monitoring pins
• Interconnect matrix: 3 bus matrices (1× AXI, 2× AHB); bridges (5× AHB2APB, 3× AXI2AHB)
• DMA controllers: 5 (1× high-speed general-purpose MDMA, 2× dual-port DMA with FIFO and request routing, 1× basic DMA with request routing, 1× dedicated basic DMA for DFSDM)
• Communication peripherals: Up to 35 (4× I2C FM+, 5× USART/5× UART with ISO7816, etc., 6× SPI including 4× with I2S, 2× SAI, SPDIFRX, SWPMI, MDIO Slave, 2× SD/SDIO/MMC, 2× CAN controllers with CAN FD and TT-CAN, 1× USB OTG, HDMI-CEC, 8–14-bit camera interface (80MHz), 8/16-bit parallel synchronous input/output slave interface)
• Analog peripherals: 11 (2× ADC up to 16-bit resolution, 24 channels, 3.6MSPS; 1 analog + 1 digital temperature sensor; 1× single-channel 12-bit DAC + 1× dual-channel 12-bit DAC; 2× ultra-low-power comparators; 2× op-amps (8MHz bandwidth); 2× sigma-delta modulator digital filters)
• Graphics: LCD-TFT controller (up to XGA resolution); Chrom-ART graphics hardware accelerator (DMA2D); hardware JPEG codec; Chrom-GRC (GFXMMU)
• Timers and watchdogs: Up to 19 timers + 2 watchdogs (2× 32-bit timers, 2× 16-bit advanced motor control timers, 10× 16-bit general-purpose timers, 3× 16-bit low-power timers, 2× watchdogs, 1× SysTick, RTC with sub-second accuracy and hardware calendar)
• Debug: SWD and JTAG interfaces; 4KB embedded trace buffer; 1× 32-bit NIST SP800-90B compliant true random number generator; 96-bit unique ID; all packages ECOPACK2 compliant
• Packages: LQFP64 (10×10mm), LQFP100 (14×14mm), LQFP144 (20×20mm), LQFP176 (24×24mm), TFBGA100 (8×8mm), TFBGA216 (13×13mm), TFBGA225 (13×13mm), UFBGA169 (7×7mm), UFBGA176+25 (10×10mm), WLCSP132 (4.57×4.37mm)