STM32H7B3ZIT6Q

The STM32H7B3xI microcontroller features a 32-bit Arm® Cortex®-M7 core running at up to 280 MHz, with 2MB Flash, 1.4MB RAM, 46 communication and analog interfaces, a switched-mode power supply (SMPS), and cryptographic capabilities. Available in multiple package options: LQFP64 (10×10 mm), LQFP100 (14×14 mm), LQFP144 (20×20 mm), LQFP176 (24×24 mm), TFBGA100 (8×8 mm), TFBGA216 (13×13 mm), TFBGA225 (13×13 mm), UFBGA169 (7×7 mm), UFBGA176+25 (10×10 mm), and WLCSP132 (4.57×4.37 mm). All packages comply with ECOPACK2 standards.

Key features

• Includes ST state-of-the-art patented technology
• 32-bit Arm Cortex-M7 core with double-precision FPU and L1 cache: 16 Kbytes of data and 16 Kbytes of instruction cache allowing to fill one cache line in a single access from the 128-bit embedded Flash memory; frequency up to 280 MHz, MPU, 599 DMIPS/ 2.14 DMIPS/MHz (Dhrystone 2.1), and DSP instructions
• 2 Mbytes of Flash memory with read while write support, plus 1 Kbyte of OTP memory
• ~1.4 Mbytes of RAM: 192 Kbytes of TCM RAM (inc. 64 Kbytes of ITCM RAM + 128 Kbytes of DTCM RAM for time critical routines), 1.18 Mbytes of user SRAM, and 4 Kbytes of SRAM in Backup domain
• 2x Octo-SPI memory interfaces with on-the-fly decryption, I/O multiplexing and support for serial PSRAM/NOR, Hyper RAM/Flash frame formats, running up to 140 MHz in SRD mode and up to 110 MHz in DTR mode
• Flexible external memory controller with up to 32-bit data bus: SRAM, PSRAM, NOR Flash memory clocked up to 125 MHz in Synchronous mode SDRAM/LPSDR SDRAM 8/16-bit NAND Flash memories
• CRC calculation unit
• ROP, PC-ROP, active tamper, secure firmware upgrade support, Secure access mode
• Up to 168 I/O ports with interrupt capability Fast I/Os capable of up to 133 MHz Up to 164 5-V-tolerant I/Os
• Stop: down to 32 μA with full RAM retention Standby: 2.8 μA (Backup SRAM OFF, RTC/LSE ON, PDR OFF) VBAT: 0.8 μA (RTC and LSE ON)
• Internal oscillators: 64 MHz HSI, 48 MHz HSI48, 4 MHz CSI, 32 kHz LSI External oscillators: 4 - 50 MHz HSE, 32.768 kHz LSE 3x PLLs (1 for the system clock, 2 for kernel clocks) with fractional mode
• 2 separate power domains, which can be independently clock gated to maximize power efficiency: CPU domain (CD) for Arm Cortex core and its peripherals, which can be independently switched in Retention mode Smart run domain (SRD) for reset and clock control, power management and some peripherals
• 1.62 to 3.6 V application supply and I/Os
• POR, PDR, PVD and BOR
• Dedicated USB power embedding a 3.3 V internal regulator to supply the internal PHYs
• Dedicated SDMMC power supply
• High power efficiency SMPS step-down converter regulator to directly supply VCORE or an external circuitry
• Embedded regulator (LDO) with configurable scalable output to supply the digital circuitry
• Voltage scaling in Run and Stop mode
• Backup regulator (~0.9 V)
• Vbat battery operating mode with charging capability
• CPU and domain power state monitoring pins
• 3 bus matrices (1 AXI and 2 AHB) Bridges (5x AHB2APB, 3x AXI2AHB)
• 5 DMA controllers to unload the CPU
• 4x I2C FM+ interfaces (SMBus/PMBus)
• 5x USART/5x UARTs (ISO7816 interface, LIN, IrDA, modem control) and 1x LPUART
• 6x SPIs, including 4 with muxed full-duplex I2S audio class accuracy via internal audio PLL or external clock and 1x SPI/I2S in LP domain (up to 125 MHz)
• 2x SAIs (serial audio interface)
• SPDIFRX interface
• SWPMI single-wire protocol master interface
• MDIO Slave interface
• 2x SD/SDIO/MMC interfaces (up to 133 MHz)
• 2x CAN controllers: 2 with CAN FD, 1 with time-triggered CAN (TT-CAN)
• 1x USB OTG interfaces (1HS/FS)
• HDMI-CEC
• 8- to 14-bit camera interface up to 80 MHz
• 8-/16-bit parallel synchronous data input/output slave interface (PSSI)
• 2x ADCs with 16-bit max. resolution (up to 24 channels, up to 3.6 MSPS)
• 1x analog and 1x digital temperature sensors
• 1x 12-bit single-channel DAC (in SRD domain) + 1x 12-bit dual-channel DAC
• 2x ultra-low-power comparators
• 2x operational amplifiers (8 MHz bandwidth)
• 2x digital filters for sigma delta modulator (DFSDM), 1x with 8 channels/8 filters and 1x in SRD domain with 2 channels/1 filter
• LCD-TFT controller up to XGA resolution
• Chrom-ART graphical hardware Accelerator (DMA2D) to reduce CPU load
• Hardware JPEG Codec
• Chrom-GRC (GFXMMU)
• 2x32-bit timers with up to 4 IC/OC/PWM or pulse counter and quadrature (incremental) encoder input (up to 280 MHz)
• 2x16-bit advanced motor control timers (up to 280 MHz)
• 10x 16-bit general-purpose timers (up to 280 MHz)
• 3x16-bit low-power timers (up to 280 MHz)
• 2x watchdogs (independent and window)
• 1x SysTick timer
• RTC with sub-second accuracy and hardware calendar
• AES chaining modes: ECB,CBC,CTR,GCM,CCM for 128, 192 or 256
• HASH (MD5, SHA-1, SHA-2), HMAC
• 2x OTFDEC AES-128 in CTR mode for Octo-SPI memory encryption/decryption
• 1x32-bit, NIST SP 800-90B compliant, true random generator
• SWD and JTAG interfaces
• 4 KB Embedded Trace Buffer
• 96-bit unique ID
• All packages are ECOPACK2 compliant