STM32H7R7Z8J6

Key features

• 32-bit Arm Cortex-M7 CPU with MPU and DP-FPU, L1 cache: 64-Kbyte instruction and data cache allowing 0-wait state execution from embedded flash memory and external memories, frequency up to 600 MHz, 1284 DMIPS/2.14 DMIPS/MHz (Dhrystone 2.1), and DSP instructions
• 64 Kbytes of user flash memory that can be used for user code and/or external memory configuration
• SRAM: total 620 Kbytes (548 Kbytes with optional ECC activated) organized as follows:
• 64+64 Kbytes minimum of instruction and data TCM RAM for critical real time instructions
• 384 Kbytes AXI SRAM (128 Kbytes with optional remap to TCM RAM fully activated)
• 4 Kbytes of backup SRAM (available in the lowest-power modes)
• Flexible external memory controller with up to 32-bit data bus: SRAM, PSRAM, FRAM, SDR/LPSDR, SDRAM, NOR/NAND memories
• Up to 2x octo-SPI memory interfaces or 1 octo-SPI + 1 hexa-SPI with XIF, with support for serial PSRAM/NAND/NOR, HyperRAM/HyperFlash frame formats running at up to 200 MHz
• 2x SD/SDIO/MMC interfaces
• 2x DMA controllers to offload the CPU: 2 x dual-port DMAs with FIFO and linked listed support
• Flexible life cycle scheme with debug authentication based on certificate or password (debug reopening/regression support)
• Root of trust thanks to unique boot entry and secure hide protection area (HDP)
• Secure firmware installation / update (SFI/SFU) thanks to embedded root secure services (RSS)
• Public key accelerator, with ECC verification feature only
• HASH hardware accelerator
• True random number generator, NIST SP800-90B compliant
• 96-bit unique ID
• 1 Kbyte OTP (one-time programmable)
• Active tampers
• Hardware secure storage (dedicated secure flash area)
• NeoChrom graphic processor (GPU2D) accelerating any angle rotation, scaling and perspective correct texture mapping
• Chrom-ART Accelerator (DMA2D) for enhanced graphic content creation
• Chrom-GRC (GFXMMU) allowing up to 20% of graphic resources optimization
• Hardware JPEG codec
• LCD-TFT controller supporting up to SVGA resolution
• Flexible memory controller FMC8/16 for parallel displays supporting up to WSVGA
• Digital camera parallel interface with pixel format conversion and cropping capabilities
• 1.71 V to 3.6 V application supply and I/O
• POR, PVD and BOR
• Dedicated USB power embedding a 3.3 V internal regulator to supply the internal PHYs
• Embedded regulator LDO to supply the VCORE and/or external circuitry
• High power-efficiency SMPS step-down converter regulator to directly supply VCORE and/or external circuitry
• Internal oscillators: 64 MHz HSI, 48 MHz HSI48, 4 MHz CSI, 32 kHz LSI
• External oscillators: 4 - 50 MHz HSE, 32.768 kHz LSE
• Sleep, Stop, and Standby modes
• VBAT supply for RTC, 32 x 32-bit backup registers
• 2x12-bit ADC, up to 5 SMPS in 12-bit, up to 17 channels
• 2 microphones /1 filter
• Voice activity detector (VAD) support
• Up to 152 I/O ports with interrupt capability
• CORDIC for trigonometric functions acceleration
• 23 timers: Sixteen 16-bit (including 5 x low power 16-bit timer available in stop mode, one graphic timer), four 32-bit timers, 2x watchdogs, 1x SysTick timer
• RTC with sub-second and hardware calendar with calibration (to be verified)
• Authenticated debug and flexible device lifecycle
• SWD and JTAG interfaces
• ETM with 2-Kbyte embedded trace buffer
• Up to 35 communication interfaces:
• 3x I2C FM+ (SMBus/PMBus)
• 1 x I3C interface (muxed with one I2C)
• Up to 3 USARTs (4 UARTs (ISO7816 interface, LIN, IrDA, modem control) and 2x LPUART
• 6 SPIs with 4 with muxed duplex I2S and 3x USART configured in synchronous mode (9 SPIs)
• 2x SAI (serial audio interface)
• 2 x FD-CAN
• 16-bit parallel slave synchronous interface
• SPDIF-IN interface, HDMI-CEC
• Ethernet MAC interface with DMA controller
• 1 USB Type-C/USB power delivery controller
• 1 USB OTG full-speed with embedded PHY
• 1 USB OTG high-speed with embedded PHY
• ECOPACK2 compliant packages