STM32U535CBT6Q

Key features

• Includes ST state-of-the-art patented technology
• Ultra-low-power with FlexPowerControl
• 1.71 V to 3.6 V power supply
• -40 °C to +85/125 °C temperature range
• Low-power background-autonomous mode (LPBAM): autonomous peripherals with DMA, functional down to Stop 2 mode
• VBAT mode: supply for RTC, 32x32-bit backup registers and 2-Kbyte backup SRAM
• 90 nA Shutdown mode (23 wake-up pins)
• 200 nA Standby mode (23 wake-up pins)
• 370 nA Standby mode with RTC
• 1.4 μA Stop 3 mode with 16-Kbyte SRAM
• 2.2 μA Stop 3 mode with full SRAM
• 3.0 μA Stop 2 mode with 16-Kbyte SRAM
• 4.6 μA Stop 2 mode with full SRAM
• 16.3 μA/MHz Run mode @ 3.3 V
• Arm 32-bit Cortex-M33 CPU with TrustZone, MPU, DSP, and FPU
• 8-Kbyte instruction cache allowing 0-wait-state execution from flash and external memories: up to 160 MHz, 240 DMIPS
• 4-Kbyte data cache for external memories
• Embedded regulator (LDO) and SMPS step-down converter supporting switch on-the-fly and voltage scaling
• 1.5 DMIPS/MHz (Dhrystone 2.1)
• 651 CoreMark (4.07 CoreMark/MHz)
• 464 ULPMark-CP
• 125 ULPMark-PP
• 54 ULPMark-CM
• 137000 SecureMark-TLS
• Up to 512-Kbyte flash memory with ECC, 2 banks read-while-write, and 100 kcycles
• 274-Kbyte SRAM including up to 64-Kbyte SRAM with ECC ON
• 1 Octo-SPI memory interface
• Arm TrustZone and securable I/Os, memories and peripherals
• Flexible life cycle scheme with RDP and password protected debug
• Root of trust thanks to unique boot entry and secure hide protection area (HDP)
• Secure firmware installation (SFI) thanks to embedded root-secure services (RSS)
• Secure firmware upgrade support with TF-M
• HASH hardware accelerator
• True random number generator, NIST SP800-90B compliant
• 96-bit unique ID
• 512-byte OTP (one-time programmable)
• Active tampers
• 4 to 50 MHz crystal oscillator
• 32 kHz crystal oscillator for RTC (LSE)
• Internal 16 MHz factory-trimmed RC (±1%)
• Internal low-power 32 kHz RC (±5%)
• 2 internal multispeed 100 kHz to 48 MHz oscillators, including one auto-trimmed by LSE (better than ±0.25% accuracy)
• Internal 48 MHz with clock recovery
• 3 PLL for system clock, USB, audio, ADC
• Up to 82 fast I/Os with interrupt capability most 5V-tolerant and up to 14 I/Os with independent supply down to 1.08 V
• Up to 17 timers and 2 watchdogs
• 2 16-bit advanced motor-control, 4 32-bit, 5 16-bit, 4 low-power 16-bit (available in Stop mode), 2 SysTick timers and 2 watchdogs
• RTC with hardware calendar and calibration
• Up to 19 communication peripherals
• 1 USB full-speed selectable host or device controller
• 1 SAI (serial-audio interface)
• 4 I²C FM+(1 Mbit/s), SMBus/PMBus
• 5 USART/UART/LPUART (SPI, ISO 7816, LIN, IrDA, modem)
• 3 SPI with OCTOSPI with USART
• 1 CAN FD controller
• 1 SDMMC interface
• 1 multi-function digital filter (2 filters) + 1 audio digital filter with sound-activity detection
• Parallel synchronous slave interface
• 16- and 4-channel DMA controllers, functional in Stop mode
• 1 digital camera interface
• CORDIC for trigonometric functions acceleration
• Filter mathematical accelerator (FMAC)
• Up to 20 capacitive sensing channels
• Support touch key, linear and rotary touch sensors
• Rich analog peripherals (independent supply)
• 14-bit ADC 2.5-Msps with hardware oversampling
• 12-bit ADC 2.5-Msps, with hardware oversampling, autonomous in Stop 2 mode
• 2 12-bit DAC, low-power sample and hold
• 1 operational amplifier with built-in PGA
• 1 ultra-low-power comparator
• CRC calculation unit
• Development support: serial-wire debug (SWD), JTAG, Embedded Trace Macrocell (ETM)
• ECOPACK2 compliant packages