STM8S103F2P3TR

This is a microcontroller based on the STM8 core, featuring a Harvard architecture and 3-stage pipeline with an extended instruction set, supporting multiple memory configurations, flexible clock and power management, rich timer and communication interfaces, robust I/O, and a 10-bit ADC.

Key features

• 16MHz advanced STM8 core with Harvard architecture and 3-stage pipeline Extended instruction set
• Program memory: 8 Kbyte Flash; data retention 20 years at 55°C after 10k cycle
• Data memory: 640 byte true data EEPROM; endurance 300k cycle
• RAM: 1 Kbyte
• 2.95 to 5.5 V operating voltage
• Flexible clock control, 4 master clock sources
• Low power crystal resonator oscillator
• External clock input
• Internal, user-trimmable 16 MHz RC
• Internal low-power 128 kHz RC
• Clock security system with clock monitor
• Power management:
• Low-power modes (wait, active-halt, halt)
• Switch-off peripheral clocks individually
• Permanently active, low-consumption poweron and power-down reset
• Nested interrupt controller with 32 interrupts
• Up to 27 external interrupts on 6 vectors
• Advanced control timer: 16-bit, 4 CAPCOM channels, 3 complementary outputs, dead-time insertion and flexible synchronization
• 16-bit general purpose timer, with 3 CAPCOM channels (IC, OC or PWM)
• 8-bit basic timer with 8-bit prescaler
• Auto wake-up timer
• Window watchdog and independent watchdog timers
• UART with clock output for synchronous operation, SmartCard, IrDA, LIN master mode
• SPI interface up to 8 Mbit/s
• I2C interface up to 400 kbit/s
• 10-bit, ±1 LSB ADC with up to 5 multiplexed channels, scan mode and analog watchdog
• Up to 28 I/Os on a 32-pin package including 21 high sink outputs
• Highly robust I/O design, immune against current injection
• 96-bit unique key for each device