STM8S207S8T6C

The product features an advanced STM8 core with Harvard architecture and a 3-stage pipeline, supporting an extended instruction set.

Key features

• Core
• Max fCPU: up to 24 MHz, 0 wait states @ fCPU ≤ 16 MHz
• Advanced STM8 core with Harvard architecture and 3 - stage pipeline
• Extended instruction set
• Max 20 MIPS @ 24 MHz
• Memories
• Program: up to 128 Kbytes Flash; data retention 20 years at 55°C after 10 kcycles
• Data: up to 2 Kbytes true data EEPROM; endurance 300 kcycles
• RAM: up to 6 Kbytes
• 2.95 to 5.5 V operating voltage
• Flexible clock control:
• Low power crystal resonator oscillator
• External clock input
• Internal, user - trimmable 16 MHz RC
• Internal low power 128 kHz RC
• Clock security system with clock monitor
• Power management:
• Wait, active - halt, & halt low power modes
• Peripheral clocks switched off individually
• Permanently active, low consumption power - on and power - down reset
• Interrupt management
• Nested interrupt controller with 32 interrupts
• Up to 37 external interrupts on 6 vectors
• Timers
• 2x 16 - bit general purpose timers, with 2 + 3 CAPCOM channels (IC, OC or PWM)
• Advanced control timer: 16 - bit, 4 CAPCOM channels, 3 complementary outputs, deadtime insertion and flexible synchronization
• 8 - bit basic timer with 8 - bit prescaler
• Auto wakeup timer
• Window watchdog, independent watchdog
• Communications interfaces
• High speed 1 Mbit/s active beCAN 2.0B
• UART with clock output for synchronous operation - LIN master mode
• UART with LIN 2.1 compliant, master/slave modes and automatic resynchronization
• SPI interface up to 10 Mbit/s
• I²C interface up to 400 Kbit/s
• 10 - bit ADC with up to 16 channels
• Up to 68 I/Os on an 80 - pin package, including 18 high sink outputs
• Highly robust I/O design, immune against current injection
• Development support: Single wire interface module (SWIM) and debug module (DM)