TMS5702124DZWTQQ1

The TMS570LS31x4/21x4 devices are high-performance automotive-grade microcontrollers designed for safety systems. The safety architecture includes: dual-core CPUs operating in lockstep mode; CPU and memory built-in self-test (BIST) logic; ECC on flash and data SRAM; parity on peripheral memory; and loopback functionality on peripheral I/Os. The TMS570LS31x4/21x4 devices integrate an ARM Cortex-R4F floating-point CPU, which delivers an efficient 1.66 DMIPS/MHz and is configurable to run at up to 180 MHz, providing up to 298 DMIPS. The devices support the word-invariant big-endian [BE32] format. The TMS570LS31x4/21x4 devices feature up to 3 MB of integrated flash and up to 256 KB of data RAM, both supporting single-bit error correction and double-bit error detection. The on-chip flash memory is a non-volatile, electrically erasable and programmable memory with a 64-bit wide data bus interface. For all read, program, and erase operations, the flash operates from a 3.3 V supply (same level as the I/O supply). In pipeline mode, the flash operates at system clock frequencies up to 180 MHz. The SRAM supports single-cycle read and write access in byte, half-word, word, and double-word modes. The TMS570LS31x4/21x4 devices feature peripherals tailored for real-time control applications, including 2 Next Generation High End Timer (N2HET) timing coprocessors and 2 12-bit ADCs supporting up to 24 inputs each. N2HET1 is an advanced intelligent timer that provides precise timing capabilities for real-time applications. The timer is software-controlled, employs a reduced instruction set, and features a dedicated timer micromachine with an associated I/O port. N2HET can be used for PWM output, capture or compare input, and GPIO. N2HET is particularly well-suited for applications requiring multiple sensor inputs and precisely timed pulses to drive actuators. A High End Timer Transfer Unit (HTU) performs DMA-type transfers of N2HET data to and from main memory. A Memory Protection Unit (MPU) is integrated within the HTU. The devices include 2 MibADCs with 12-bit resolution, each with 24 channels and a buffer RAM protected by 64-word parity. MibADC channels can be converted individually or grouped by software for sequential conversion sequences. 16 channels can be shared between the two MibADCs. There are three independent groups. Each sequence can be converted once when triggered or configured for continuous conversion mode. The devices provide multiple communication interfaces: 3 MibSPIs, 2 SPIs, 1 LIN, 1 SCI, 3 DCANs, and 1 I2C. SPI provides a convenient method for high-speed serial communication between shift-register-type devices. LIN supports the Local Interconnect Standard 2.0 and can be used as a full-duplex UART using the standard Non-Return-to-Zero (NRZ) format. DCAN supports the CAN 2.0 (A and B) protocol standard and uses a serial, multi-master communication protocol that efficiently supports distributed real-time control at communication rates up to 1 Mbps. DCAN is well-suited for systems operating in noisy and harsh environments (e.g., automotive networking and industrial applications) that require reliable serial communication or multiplexed wiring. The I2C module is a multi-master communication module that provides an interface between the microcontroller and I2C-compatible devices over the I2C serial bus. The I2C supports speeds of 100 Kbps and 400 Kbps. The Frequency Modulated Phase-Locked Loop (FMPLL) clock module is used to multiply an external frequency reference to a higher frequency for internal use. The device includes two FMPLL modules. When enabled, these modules provide two of seven possible clock sources to the Global Clock Module (GCM). The GCM manages the mapping between available clock sources and the device clock domains. The device also includes an External Clock Prescaler (ECP) module that, when enabled, outputs a continuous external clock on the ECLK pin/ball. The ECLK frequency is a user-programmable ratio of the peripheral interface clock (VCLK) frequency. This externally monitorable low-frequency output serves as an indicator of the device's operating frequency. The Direct Memory Access (DMA) controller features 16 channels, 32 control packets, and parity protection for its memory. An MPU is integrated within the DMA to restrict DMA access to designated memory regions and protect the rest of the memory system from DMA faults. The Error Signaling Module (ESM) monitors all device errors and, upon fault detection, determines whether to generate an interrupt or assert an external ERROR pin. The ERROR pin can be externally monitored as an indicator of fault conditions within the microcontroller. The External Memory Interface (EMIF) provides off-chip expansion capability, enabling interfacing with synchronous DRAM (SDRAM) devices, asynchronous memory, peripherals, or FPGA devices. Several interfaces are implemented to enhance application code debug capability. In addition to the built-in ARM Cortex-R4F CoreSight debug features, an External Trace Macrocell (ETM) provides instruction and data trace of program execution. For instrumentation purposes, a RAM Trace Port (RTP) module is implemented to support high-speed tracing of RAM and peripherals accessed by the CPU or any other master. A Data Modification Module (DMM) provides the ability to write external data to device memory. RTP and DMM have no or minimal impact on application code execution time. A Parameter Overlay Module (POM) can reroute flash accesses to internal memory or EMIF. This rerouting enables dynamic calibration of parameters and tables against production code without requiring code rebuilds to explicitly access RAM or halting the processor to re-program data flash. With integrated safety features and an extensive selection of communication and control peripherals, the TMS570LS31x4/21x4 devices are ideal solutions for high-performance real-time control applications with safety-critical requirements.

Applications

• Braking systems (ABS and ESC)
• Electric power steering
• HEV and EV inverter systems
• Battery management systems
• Active driver assistance systems
• Rail transportation
• Off-road vehicles

Key features

• High-performance MCU for safety-critical applications
• Dual CPUs running in lockstep
• ECC on flash and RAM interfaces
• Built-in CPU and on-chip RAM self-test
• Error Signaling Module (ESM) with error pin
• Voltage and clock monitoring
• ARM Cortex-R4F 32-bit RISC CPU
• High-efficiency 1.66 DMIPS/MHz with 8-stage pipeline
• FPU supporting single- and double-precision floating-point
• 12-region Memory Protection Unit (MPU)
• Open architecture with third-party support
• Up to 180 MHz system clock
• Core supply voltage (VCC): 1.2V nominal
• I/O supply voltage (VCCOI): 3.3V nominal
• ADC supply voltage (VCCAD): 3.0 to 5.25V
• Up to 3MB program flash with ECC
• Up to 256KB RAM with ECC
• ECC for emulated EEPROM
• 16-bit external memory interface
• Consistent memory map across the family
• Real-Time Interrupt (RTI) OS timer
• 96-channel Vector Interrupt Module (VIM)
• 2-channel Cyclic Redundancy Checker (CRC)
• JTAG security module
• Trace and calibration features
• Embedded Trace Macrocell (ETM-R4)
• Data Modification Module (DMM)
• RAM Trace Port (RTP)
• Parameter Overlay Module (POM)
• Multiple communication interfaces
• 3 CAN controllers (DCAN)
• 64 mailboxes, each with parity protection
• Compatible with CAN protocol version 2.0B
• LIN interface controller
• Compatible with LIN protocol version 2.1
• Configurable as a second SCI
• Standard Serial Communication Interface (SCI)
• I2C
• 3 Multi-buffered SPI (MibSPI)
• 128 words, each with parity protection
• 2 standard SPI
• 2 Next Generation High-End Timer (N2HET) modules
• N2HET1: 32 programmable channels
• N2HET2: 18 programmable channels
• 160-word instruction RAM, each with parity protection
• Hardware angle generator included in each N2HET
• Dedicated Transfer Unit with MPU for each N2HET (HTU)
• 2 multi-buffered 10- or 12-bit ADC modules
• ADC1: 24 channels
• ADC2: 16 channels shared with ADC1
• 64 result buffers, each with parity protection
• 10 GPIO pins capable of generating interrupts
• Packages
• 144-pin QFP (PGE) [Green]
• 337-ball BGA (ZWT) [Green]