TMS5702135DPGEQQ1

The TMS570LS31x5/21x5 devices are high-performance automotive-grade microcontrollers designed for safety systems. The safety architecture includes: dual-core CPUs operating in lockstep mode; CPU and memory built-in self-test (BIST) logic; ECC on flash and data SRAM; parity on peripheral memory; and loopback capability on peripheral I/O. The TMS570LS31x5/21x5 devices integrate an ARM Cortex-R4F floating-point CPU, which delivers an efficient 1.66 DMIPS/MHz and is configurable to run at up to 180 MHz, providing up to 298 DMIPS. These devices support the word-invariant big-endian [BE32] format. The TMS570LS31x5/21x5 devices feature up to 3MB of integrated flash memory and up to 256KB of data RAM, both supporting single-bit error correction and double-bit error detection. The on-chip flash memory is a non-volatile, electrically erasable and programmable memory with a 64-bit wide data bus interface. For all read, program, and erase operations, the flash operates from a 3.3V supply (same level as the I/O supply). In pipeline mode, the flash operates at system clock frequencies up to 180 MHz. The SRAM supports single-cycle read and write access in byte, half-word, word, and double-word modes. The TMS570LS31x5/21x5 devices feature peripherals tailored for real-time control applications, including 2 Next Generation High-End Timer (N2HET) timing coprocessors and 2 12-bit ADCs supporting up to 24 inputs each. N2HET1 is an advanced intelligent timer providing precision timing for real-time applications. It is software-controlled, employs a reduced instruction set, and features a dedicated timer micromachine and an associated I/O port. N2HET can be used for PWM output, capture or compare input, and GPIO. N2HET is especially suited for applications requiring multiple sensor inputs and driving actuators with complex and precise timing pulses. A High-End Timer Transfer Unit (HTU) performs DMA-type transfers of N2HET data to and from main memory. An MPU is built into the HTU. The device includes 2 12-bit resolution MibADCs, each with 24 channels and a buffer RAM protected by 64-word parity. MibADC channels can be converted individually or grouped by software for sequential conversion sequences. 16 channels can be shared between the two MibADCs. There are three independent groups. Each sequence can be converted once when triggered or configured for continuous conversion mode. The device provides multiple communication interfaces: 3 MibSPIs, 2 SPIs, 1 LIN, 1 SCI, 3 DCANs, 1 I2C, and 1 FlexRay controller. SPI provides a convenient method for high-speed serial communication between shift-register-type devices. LIN supports the Local Interconnect standard 2.0 and can be used as a full-duplex UART using the standard non-return-to-zero (NRZ) format. DCAN supports the CAN 2.0 (A and B) protocol standard and uses a serial, multi-master communication protocol that efficiently supports distributed real-time control at communication rates up to 1 Mbps. DCAN is well suited for systems operating in noisy and harsh environments (e.g., automotive network interconnects and industrial applications) that require reliable serial communication or multiplexed wiring. The FlexRay controller uses a dual-channel serial, fixed time base, multi-master communication protocol with a communication rate of 10 Mbps per channel. A FlexRay Transfer Unit (FTU) enables data transfers between FlexRay and the CPU main memory. Transfers are protected by a dedicated built-in MPU. The I2C module is a multi-master communication module that provides an interface between the microcontroller and I2C-compatible devices over the I2C serial bus. This I2C supports speeds of 100 Kbps and 400 Kbps. The Frequency Modulated Phase-Locked Loop (FMPLL) clock module is used to multiply an external frequency reference to a higher frequency for internal use. There are two FMPLL modules on this device. When enabled, these modules provide two of seven possible clock sources to the Global Clock Module (GCM). The GCM manages the mapping between available clock sources and the device clock domains. The device also includes an External Clock Prescaler (ECP) module, which outputs a continuous external clock on the ECLK pin/ball when enabled. The ECLK frequency is a user-programmable ratio of the peripheral interface clock (VCLK) frequency. This externally monitorable low-frequency output serves as an indicator of the device's operating frequency. The DMA controller has 16 channels, 32 control data packets, and parity protection for its memory. An MPU is built into the DMA to restrict DMA access to designated memory regions and protect the remainder of the memory system from DMA faults. The Error Signaling Module (ESM) monitors all device errors and, upon detecting a fault, determines whether to generate an interrupt or assert an external ERROR pin. This ERROR pin can be monitored externally as an indicator of fault conditions within the microcontroller. The External Memory Interface (EMIF) provides off-chip expansion capability, enabling interfacing with synchronous DRAM (SDRAM) devices, asynchronous memory, peripherals, or FPGA devices. Several interfaces are implemented to enhance the debuggability of application code. In addition to the built-in ARM Cortex-R4F CoreSight debug features, an External Trace Macrocell (ETM) provides instruction and data tracing of program execution. For instrumentation purposes, a RAM Trace Port (RTP) module is implemented to support high-speed tracing of RAM and peripherals accessed by the CPU or any other master. A Data Modification Module (DMM) provides the capability to write external data into device memory. RTP and DMM have no or minimal impact on application code execution time. A Parameter Overlay Module (POM) can reroute flash accesses to internal memory or EMIF. This rerouting enables dynamic calibration of parameters and tables against production code without requiring code rebuilds to explicitly access RAM or stopping the processor to re-program the data flash. With integrated safety features and an extensive selection of communication and control peripherals, the TMS570LS31x5/21x5 devices are an ideal solution for high-performance real-time control applications with safety-critical requirements.

Applications

• Braking systems (ABS and ESC)
• Electric power steering
• HEV and EV inverter systems
• Battery management systems
• Active driver assistance systems
• Rail transportation
• Off-road vehicles

Key features

• High-performance automotive-grade MCU for safety-critical applications
• Dual CPU cores running in lockstep
• ECC on flash and RAM interfaces
• Built-in CPU and on-chip RAM self-test
• Error Signaling Module (ESM) with error pin
• Voltage and clock monitoring
• ARM Cortex-R4F 32-bit RISC CPU, 1.66 DMIPS/MHz with 8-stage pipeline
• FPU supporting single- and double-precision floating-point operations
• 12-region MPU with open architecture and third-party support
• Up to 180MHz system clock
• Core supply voltage (VCC): 1.2V nominal
• I/O supply voltage (VCCOI): 3.3V nominal
• ADC supply voltage (VCCAD): 3.0 to 5.25V
• Up to 3MB program flash with ECC
• Up to 256KB RAM with ECC
• ECC-protected emulated EEPROM
• Consistent memory map across the family
• Real-Time Interrupt (RTI) OS timer
• 96-channel Vector Interrupt Module (VIM)
• 2-channel Cyclic Redundancy Checker (CRC)
• Embedded Trace Macrocell (ETM-R4)
• Data Modification Module (DMM)
• RAM Trace Port (RTP)
• Parameter Overlay Module (POM)
• N2HET1: 32 programmable channels
• N2HET2: 18 programmable channels
• 160-word instruction RAM, each with parity protection
• Hardware angle generator per N2HET
• Dedicated Transfer Unit with MPU per N2HET (HTU)