74LVC1G10GM,115

The 74LVC1G10 provides a low-power, low-voltage single 3-input NAND gate. The inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of this device in a mixed 3.3 V and 5 V environment. Schmitt trigger action at all inputs makes the circuit tolerant to slower input rise and fall time. This device is fully specified for partial power-down applications using IOFF. The IOFF circuitry disables the output, preventing the damaging backflow current through the device when it is powered down.

Applications

• Mixed 3.3V and 5V environments
• Direct TTL-level interface
• Partial power-down applications

Key features

• Wide supply voltage range from 1.65 V to 5.5 V
• High noise immunity
• ±24 mA output drive (VCC = 3.0 V)
• CMOS low power dissipation
• Latch-up performance exceeds 250 mA
• Direct interface with TTL levels
• Inputs accept voltages up to 5 V
• IOFF circuitry provides partial Power-down mode operation
• Complies with JEDEC standard:
• JESD8 - 7 (1.65 V to 1.95 V)
• JESD8 - 5 (2.3 V to 2.7 V)
• JESD8C (2.7 V to 3.6 V)
• JESD36 (4.5 V to 5.5 V)
• ESD protection:
• HBM: ANSI/ESDA/JEDEC JS - 001 class 2 exceeds 2000 V
• CDM: ANSI/ESDA/JEDEC JS - 002 class C3 exceeds 1000 V
• Multiple package options
• Specified from -40 °C to +85 °C and -40 °C to +125 °C