CD4012BPWR

3V~18V 90ns@15V,50pF 1uA TSSOP-14 Gates and Inverters RoHS

TSSOP-14ROHS3 CompliantActive

CMOS NAND GATES High-Voltage Types

Manufacturer: TI
Manufacturer part #: CD4012BPWR
Store part #: C2682012
Package / case: TSSOP-14
Category: Gates and Inverters
Packaging: Tape & Reel (TR)

Datasheet (PDF)

Every Order Guarantee

100% Authentic · 30-Day Return or Replacement · policy

225 in stock

#C2682012

Stock & price checked 8 days ago

Quantity	Unit price	Pack price
1+	₹65.01	₹65.01
10+	₹63.49	₹634.90
30+	₹62.42	₹1,872.60
100+	₹61.56	₹6,156.00

Quantity (min 1)

1 × ₹65.01

₹65.01

excl. GST

₹76.71 incl. 18% GST

Need volume or a scheduled delivery? Request a quote

Dispatch in 15-18 working days
GST invoice with every order
Standard pack: 2,000 per reel

CD4012BPWR

₹65.01 for 1 + GST

Need this with the rest of your board? Upload the BOM — we price every line.Upload BOM

Specifications

Logic Family: 4000B Series
Voltage - Supply: 3V~18V
Output Logic Level - Low: 50mV
Propagation Delay: 90ns@15V,50pF
Input Logic Level - High: 3.5V~11V
Input Logic Level - Low: 1.5V~4V
Operating Temperature: -55℃~+125℃
Output Logic Level - High: 4.95V;9.95V;14.95V
Quiescent Current(Iq): 1uA
Number of Channels: 2;4
Current - Output High(IOH): 3.4mA
Current - Output Low(IOL): 3.4mA

Packaging & compliance

RoHS: ROHS3 Compliant
Lifecycle: Active
ECCN: EAR99
Packaging: Tape & Reel (TR)
Standard pack: 2,000 / Reel
Sold per: Piece
Minimum order: 1
Unit weight: 0.204 g

Overview

CD4011B, CD4012B, and CD4023B NAND gates provide the system designer with direct implementation of the NAND function and supplement the existing family of CMoS gates. All inputs and outputs are buffered. The CD4011B, CD4012B, and CD4023B types are supplied in 14 - lead hermetic dual - in - line ceramic packages (F3A suffix), 14 - lead dual - in - line plastic packages (E suffix), 14 - lead small - outline packages (M, MT, M96, and NSR suffixes), and 14 - lead thin shrink small - outline packages (PWR suffix). The CD4011B and CD4023B types also are supplied in 14 - lead thin shrink small - outline packages (PW suffix).

Key features

Propagation delay time = ±50 ns (typ.) at cL = 50 pF, VDD = 10 V
Buffered inputs and outputs
Standardized symmetrical output characteristics
Maximum input current of ±1 μA at 18 V over full package temperature range; 100 nA at 18 V and 25°C
100% tested for quiescent current at 20 V
5 - V, 10 - V, and 15 - V parametric ratings
Noise margin (over full package temperature range):
1 V at VDD = 5 V
2 V at VDD = 10 V
2.5 V at VDD = 15 V
Meets all requirements of JEDEC Tentative Standard No. 13B, "Standard Specifications for Description of 'B' Series CMOs Devices"