PIC18F26J11T-I/SS

Key features

• Deep Sleep mode: CPU off, Peripherals off, Currents Down to 13 nA and 850 nA with RTCC - Able to wake-up on external triggers, programmable WDT or RTCC alarm - Ultra Low-Power Wake-up (ULPWU)
• Sleep mode: CPU off, Peripherals off, SRAM on, Fast Wake-up, Currents Down to 105 nA Typical
• Idle: CPU off, Peripherals on, Currents Down to 2.3 μA Typical
• Run: CPU on, Peripherals on, Currents Down to 6.2 μA Typical
• Timer1 Oscillator/w RTCC: 1 μA, 32 kHz Typical
• Watchdog Timer: 813 nA, 2V Typical
• 5.5V Tolerant Inputs (digital only pins)
• Low-Power, High-Speed CMOS Flash Technology
• C Compiler Optimized Architecture for Re-Entrant Code
• Priority Levels for Interrupts
• Self-Programmable under Software Control
• 8x8 Single-Cycle Hardware Multiplier
• Extended Watchdog Timer (WDT): Programmable period from 4 ms to 131s
• Single-Supply In-Circuit Serial Programming (ICSP) via Two Pins
• In-Circuit Debug (ICD) with Three Breakpoints via Two Pins
• Operating Voltage Range of 2.0V to 3.6V
• On-Chip 2.5V Regulator
• Flash Program Memory of 10,000 Erase/Write Cycles Minimum and 20-Year Data Retention
• Peripheral Pin Select: Allows independent I/O mapping of many peripherals Continuous hardware integrity checking and safety interlocks prevent unintentional configuration changes
• Hardware Real-Time Clock and Calendar (RTCC): Provides clock, calendar and alarm functions
• High-Current Sink/Source 25 mA/25 mA (PO)